https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729649#M113473 <HTML><HEAD></HEAD><BODY><P><SPAN>about imx6 DDR3 design，there is no need to connect DRAM_SDCLK_0 and DRAM_SDCLK_1 with CK of DDR3？</SPAN></P><P><SPAN>iMX6 SabreSD board do not use&nbsp; DRAM_SDCLK_0 and DRAM_SDCLK_1 ,but some other board use them ,i want to know what is the effect of DRAM_SDCLK_0 and DRAM_SDCLK_1? thanks</SPAN></P></BODY></HTML> Mon, 30 Oct 2017 08:51:34 GMT dqz 2017-10-30T08:51:34Z https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729649#M113473 <HTML><HEAD></HEAD><BODY><P><SPAN>about imx6 DDR3 design，there is no need to connect DRAM_SDCLK_0 and DRAM_SDCLK_1 with CK of DDR3？</SPAN></P><P><SPAN>iMX6 SabreSD board do not use&nbsp; DRAM_SDCLK_0 and DRAM_SDCLK_1 ,but some other board use them ,i want to know what is the effect of DRAM_SDCLK_0 and DRAM_SDCLK_1? thanks</SPAN></P></BODY></HTML> Mon, 30 Oct 2017 08:51:34 GMT https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729649#M113473 dqz 2017-10-30T08:51:34Z https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729650#M113474 <HTML><HEAD></HEAD><BODY><P>Helo Dq,</P><P>clock always has to be provided to the DDR3 device. i.MX6 SabreSD uses DRAM_SDCLK_0 and DRAM_SDCLK_1. Could you please share the schematic from which you determined that those clocks are not used?</P><P></P><P>Best Regards,</P><P>Jan</P></BODY></HTML> Mon, 30 Oct 2017 09:01:52 GMT https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729650#M113474 jan_spurek 2017-10-30T09:01:52Z https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729651#M113475 <HTML><HEAD></HEAD><BODY><P><span class="lia-inline-image-display-wrapper" image-alt="捕获.PNG"><img src="https://community.nxp.com/t5/image/serverpage/image-id/11432iAE3FE6D369C28980/image-size/large?v=v2&amp;px=999" role="button" title="捕获.PNG" alt="捕获.PNG" /></span></P><P><span class="lia-inline-image-display-wrapper" image-alt="ssss.jpg"><img src="https://community.nxp.com/t5/image/serverpage/image-id/11398i2FF49A2EF5D235F2/image-size/large?v=v2&amp;px=999" role="button" title="ssss.jpg" alt="ssss.jpg" /></span></P></BODY></HTML> Mon, 30 Oct 2017 09:09:19 GMT https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729651#M113475 dqz 2017-10-30T09:09:19Z https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729652#M113476 <HTML><HEAD></HEAD><BODY><P>Hello Dq,</P><P>these pads serve as clock access points. By default the 0R resistors are not mounted and their pads are bridged by</P><P>scratching planes.</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="mnt.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/11476iDD20DB7EC2BF774C/image-size/large?v=v2&amp;px=999" role="button" title="mnt.png" alt="mnt.png" /></span></P><P></P><P>Best Regards,</P><P>Jan</P></BODY></HTML> Mon, 30 Oct 2017 09:26:18 GMT https://community.nxp.com/t5/i-MX-Processors/DRAM-SDCLK-0-and-DRAM-SDCLK-1/m-p/729652#M113476 jan_spurek 2017-10-30T09:26:18Z