topic Re: DDR3 Clock Routing in i.MX Processors

DDR3 Clock Routing

danielmelendy — Tue, 16 Jan 2018 18:11:42 GMT

Hi All,

I'm just getting started with the IMX6Quad processor (MCIMX6Q6AVT10AC) and I had a question about the DDR3 interface. What is the purpose of having two different DDR clocks (DRAM_SDCLK_0 / DRAM_SDCLK_1)? I've looked at the SABRE reference design and one clock goes to 2 of the DDR chips and one goes to the other two. Is this just for convenience? All of the other command and address lines have to be T'd to go all of the DDR chips since they only come out at a single ball... Wouldn't it be better, from a timing perspective, to use one of the clocks and T it the same as the command and address lines?

-Daniel

Re: DDR3 Clock Routing

igorpadykov — Tue, 16 Jan 2018 22:51:29 GMT

Hi Daniel

right, two i.MX6Q different DDR clocks (DRAM_SDCLK_0 / DRAM_SDCLK_1) are provided

just for convenience routing. Routing rules are described in i.MX6 System Development User’s Guide

https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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