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    <title>i.MX ProcessorsのトピックRe: Boot problems with new NAND on mx53</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727173#M113081</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Igor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I´ve checked and re-checked all BOOT_CFG words, and everything seems to be ok but...no success. I can´t boot from this NAND, but I&amp;nbsp;can write and store data, so problem is not in NAND timings or some other physical parameter of&amp;nbsp;NAND (not even in uboot/Linux source code drivers I think) , but in the way those first bytes are read&amp;nbsp;by ROM code inside MX53 board (or the way i wote them when flashed).&amp;nbsp;&lt;/P&gt;&lt;P&gt;Somebody told me about&amp;nbsp;enabling/disabling byte&amp;nbsp;swap&amp;nbsp;when NAND uboot partition is flashed, but after testing it nothing changed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With kobs-ng tool, I get a "bootstream too large" error.so before connecting a JTAG as last resort...,do&amp;nbsp;somebody know if I should also change something&amp;nbsp;in kobs-ng sources to adapt them to my new NAND flash?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Not really sure if kobs-ng will help with this. If i´m changing NAND geometry (4K+218 to 2K+64)...should&amp;nbsp;change something in NAND first bytes and how&amp;nbsp;would&amp;nbsp;they be written to flash? &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 08 Nov 2017 14:18:53 GMT</pubDate>
    <dc:creator>paulroy</dc:creator>
    <dc:date>2017-11-08T14:18:53Z</dc:date>
    <item>
      <title>Boot problems with new NAND on mx53</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727170#M113078</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all&lt;/P&gt;&lt;P&gt;We have to make our iMX53 board&amp;nbsp;boot from a new Cypress - &lt;STRONG&gt;S34ML16G202BHI003&lt;/STRONG&gt; NAND, so we set new parameters for both u-boot and kernel, as:&amp;nbsp; (datasheet)&lt;/P&gt;&lt;PRE style="background-color: #ffffff;"&gt; .end_of_table&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = false,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.manufacturer_code&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x01,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.device_code&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xd5,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.cell_technology&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NAND_DEVICE_CELL_TECH_SLC,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.chip_size_in_bytes&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 2048LL*SZ_1M,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.block_size_in_pages&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 64,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.page_total_size_in_bytes = 2*SZ_1K + 128,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.ecc_strength_in_bits&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 4,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.ecc_size_in_bytes&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 512,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.data_setup_in_ns&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 20, //tds&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.data_hold_in_ns&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 10, //tdh&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.address_setup_in_ns&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 25, //tals&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.gpmi_sample_delay_in_ns&amp;nbsp; = 6,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.tREA_in_ns&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 30,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.tRLOH_in_ns&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
.tRHOH_in_ns&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 15,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
"S34ML16G200",&lt;/PRE&gt;&lt;P&gt;and after a correct NAND flash, we see we &lt;STRONG&gt;can't boot&lt;/STRONG&gt; from NAND, but if we load u-boot with serial download to the board and tell that u-boot boot from kernel partition on new NAND,&lt;STRONG&gt; it boots&lt;/STRONG&gt; OK.&lt;/P&gt;&lt;P&gt;So,it seems NAND is working at all, but we are not able to boot from it. Old NAND was an&amp;nbsp;MT29F16G08ABACA, and we boot&amp;nbsp; OK in same board. So, doubts are:&lt;/P&gt;&lt;P&gt;- do we have to change some other parameters in u-boot to use this new nand? (apart from the ones in struct above)&lt;/P&gt;&lt;P&gt;- should the first bytes seen on nand 0x0000 position change after changing NAND? They look the same,&amp;nbsp;in spite of the change&amp;nbsp;in new NAND geometry.&lt;/P&gt;&lt;P&gt;- could some pull up resistor value soldered in NAND pins (RBB for example) cause this behaviour?.( We have same values for old and new nands)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any help is appreciated. Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 29 Oct 2017 09:08:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727170#M113078</guid>
      <dc:creator>paulroy</dc:creator>
      <dc:date>2017-10-29T09:08:35Z</dc:date>
    </item>
    <item>
      <title>Re: Boot problems with new NAND on mx53</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727171#M113079</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, I´ve seen all NAND has BOOT_CFG2[7:6] as 11 and new one should be 01, I think. So do you know how could I change that?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Oct 2017 16:17:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727171#M113079</guid>
      <dc:creator>paulroy</dc:creator>
      <dc:date>2017-10-30T16:17:05Z</dc:date>
    </item>
    <item>
      <title>Re: Boot problems with new NAND on mx53</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727172#M113080</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Paul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please refer to Table 7-11. NAND Boot eFUSE Descriptions&lt;/P&gt;&lt;P&gt;i.MX53 Reference Manual&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/reference-manual/iMX53RM.pdf" title="https://www.nxp.com/docs/en/reference-manual/iMX53RM.pdf"&gt;https://www.nxp.com/docs/en/reference-manual/iMX53RM.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;there is no formal support for 2K+128bytes nand geometry.&lt;/P&gt;&lt;P&gt;However seems this Cypress - S34ML16G202BHI003 NAND is multiplane&lt;/P&gt;&lt;P&gt;nand with every plane with 2K+64bytes nand geometry, which is supported.&lt;/P&gt;&lt;P&gt;Please check documentation:&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.cypress.com%2Fdocumentation%2Fdatasheets%2Fs34ml01g2-s34ml02g2-s34ml04g2-1-gb-2-gb-4-gb-3-v-4-bit-ecc-slc-nand-flash%3Fsource%3Dsearch%26keywords%3DS34ML01G2_04G2" rel="nofollow" target="_blank"&gt;http://www.cypress.com/documentation/datasheets/s34ml01g2-s34ml02g2-s34ml04g2-1-gb-2-gb-4-gb-3-v-4-bit-ecc-slc-nand-flash?source=search&amp;amp;keywords=S34ML01G2_04G2&lt;/A&gt;&lt;/P&gt;&lt;P&gt;So seems one can try to set BOOT_CFG1[3:2] Address Cycles 10 - 5,&lt;/P&gt;&lt;P&gt;BOOT_CFG2[7:6] Page Size 01 - 2KB + 64 Bytes (4-bit ECC).&lt;/P&gt;&lt;P&gt;For nand programming please use kobs-ng, please check&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-thread-small" data-containerid="2004" data-containertype="14" data-objectid="316154" data-objecttype="1" href="https://community.nxp.com/thread/316154"&gt;https://community.nxp.com/thread/316154&lt;/A&gt;&lt;BR /&gt;&lt;A class="jive-link-thread-small" data-containerid="2004" data-containertype="14" data-objectid="324232" data-objecttype="1" href="https://community.nxp.com/thread/324232"&gt;https://community.nxp.com/thread/324232&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Also one can try to use mfg tools :&lt;BR /&gt;Programmers (Flash, etc.) (3)&lt;BR /&gt;IMX_MFG_TOOL&lt;BR /&gt;&lt;A href="https://www.nxp.com/products/power-management/pmics/power-management-for-i.mx-application-processors/i.mx53-quick-start-board:IMX53QSB?tab=Design_Tools_Tab"&gt;https://www.nxp.com/products/power-management/pmics/power-management-for-i.mx-application-processors/i.mx53-quick-start-board:IMX53QSB?tab=Design_Tools_Tab&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Nov 2017 06:43:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727172#M113080</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-11-01T06:43:13Z</dc:date>
    </item>
    <item>
      <title>Re: Boot problems with new NAND on mx53</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727173#M113081</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Igor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I´ve checked and re-checked all BOOT_CFG words, and everything seems to be ok but...no success. I can´t boot from this NAND, but I&amp;nbsp;can write and store data, so problem is not in NAND timings or some other physical parameter of&amp;nbsp;NAND (not even in uboot/Linux source code drivers I think) , but in the way those first bytes are read&amp;nbsp;by ROM code inside MX53 board (or the way i wote them when flashed).&amp;nbsp;&lt;/P&gt;&lt;P&gt;Somebody told me about&amp;nbsp;enabling/disabling byte&amp;nbsp;swap&amp;nbsp;when NAND uboot partition is flashed, but after testing it nothing changed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With kobs-ng tool, I get a "bootstream too large" error.so before connecting a JTAG as last resort...,do&amp;nbsp;somebody know if I should also change something&amp;nbsp;in kobs-ng sources to adapt them to my new NAND flash?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Not really sure if kobs-ng will help with this. If i´m changing NAND geometry (4K+218 to 2K+64)...should&amp;nbsp;change something in NAND first bytes and how&amp;nbsp;would&amp;nbsp;they be written to flash? &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Nov 2017 14:18:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727173#M113081</guid>
      <dc:creator>paulroy</dc:creator>
      <dc:date>2017-11-08T14:18:53Z</dc:date>
    </item>
    <item>
      <title>Re: Boot problems with new NAND on mx53</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727174#M113082</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Paul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;may be useful to check&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/NXPmicro/imx-kobs" title="https://github.com/NXPmicro/imx-kobs"&gt;GitHub - NXPmicro/imx-kobs: Tool to create and write Freescale/NXP I.MX NAND boot related boot data structure to nand fl…&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Nov 2017 23:12:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Boot-problems-with-new-NAND-on-mx53/m-p/727174#M113082</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-11-08T23:12:19Z</dc:date>
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