Ethernet on ENET2 with imx6sx in u-boot

huihuang — Sun, 17 Dec 2017 05:00:45 GMT

Hi everybody,

I am using imx6sx on a costume board i connected ethernet to ENET2 with RMII and externel oscillator.

what modification i should do on u-boot to get it work?

already I set the CONFIG_FEC_ENET_DEV = 1

and CONFIG_FEC_XCV_TYPE = RMII

the result in u-boot-imx and in u-boot-fslc is: build and run but no network!

could anyone please help

thanks

Re: Ethernet on ENET2 with imx6sx in u-boot

igorpadykov — Mon, 18 Dec 2017 08:16:05 GMT

Hi Hui

one can check settings for external clock in IOMUXC_GPR_GPR1

which are defined in setup_fec() mx6sxsabresd.c

uboot-imx.git - Freescale i.MX u-boot Tree

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: Ethernet on ENET2 with imx6sx in u-boot

huihuang — Tue, 19 Dec 2017 06:32:47 GMT

Dear Igor,

thanks for the answer, but i was not lucky!

here is the SCH of PHY and SOC:

i use y-boot imx: and modified the FEC pin mux: this is part of board/freescale/mx6sxsabresd/mx6sxsabresd.c

static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_RXC__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD0__GPIO5_IO_12 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD1__GPIO5_IO_13 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD0__GPIO5_IO_18 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD1__GPIO5_IO_19 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
/*
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
*/
static iomux_v3_cfg_t const phy_control_pads[] = {
/* 25MHz Ethernet PHY Clock */
/*MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),*/

/* 50M Ethernet clock*/
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),

/* ENET PHY Power */
/*MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),*/

/* AR8031 PHY Reset */
/*MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),*/
};

static int setup_fec(int fec_id)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
int reg;

if (0 == fec_id)
/* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
else
/* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);

imx_iomux_v3_setup_multiple_pads(phy_control_pads,
ARRAY_SIZE(phy_control_pads));

/* Enable the ENET power, active low */
/*gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);*/

/* Reset AR8031 PHY */
/*gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);*/

/*
reg = readl(&anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);

return enable_fec_anatop_clock(fec_id, ENET_125MHZ);*/
return 1;
}

int board_eth_init(bd_t *bis)
{
int retval;

if (0 == CONFIG_FEC_ENET_DEV)
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
else
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));

setup_fec(CONFIG_FEC_ENET_DEV);
retval=cpu_eth_init(bis);
return retval;
}

would you please help.

thanks

i.MX ProcessorsのトピックRe: Ethernet on ENET2 with imx6sx in u-boot

Ethernet on ENET2 with imx6sx in u-boot

Re: Ethernet on ENET2 with imx6sx in u-boot

Re: Ethernet on ENET2 with imx6sx in u-boot