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    <title>topic Re: Is it possible to achieve TRM mentioned data rate in MIPI CSI ? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723836#M112549</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/titusstalin"&gt;titusstalin&lt;/A&gt;‌ :&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Did you have find out how to achieve the mentioned data rate of 800Mbps with 4-lanes?&lt;/P&gt;&lt;P&gt;I found mipi-csi2-rx maybe could not support up to 800Mbps with 4-lanes.&lt;/P&gt;&lt;P&gt;Best Regard.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 21 Aug 2020 06:50:13 GMT</pubDate>
    <dc:creator>eason-tang</dc:creator>
    <dc:date>2020-08-21T06:50:13Z</dc:date>
    <item>
      <title>Is it possible to achieve TRM mentioned data rate in MIPI CSI ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723833#M112546</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I have interfaced our 4 lane supported camera into i.MX6 board and written our own camera driver based on i.MX6 reference camera OV5640 driver.&lt;/P&gt;&lt;P&gt;TRM mentioned that MIPI CSI2 supports data rate upto 800Mbps per lane when we use 4 lane configuration and 1Gbps/lane when we use 1/2/3 lane count.&lt;/P&gt;&lt;P&gt;IMX6DQRM.pdf, page no 450.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;One MIPI/CSI-2 port- IPU receives two components per cycle from the MIPI_CSI2&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;interface. The maximum bandwidth of the interface is as follows:&lt;/STRONG&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;• 400MByte/sec for four data lanes configuration (800Mbps/lane)&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;STRONG&gt;• 375MByte/sec for 3 data lanes configuration (1000Mbps/lane)&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;• 250MByte/sec for 2 data lanes configuration (1000Mbps/lane)&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;• 125Mbyte/sec for 1 data lanes configuration (1000Mbps/lane)&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I can achieve 1Gbps/lane for 1/2/3 lane configurations as mentioned in TRM but unable to achieve 800Mbps/lane for 4 lane configuration, we are able to get 790Mbps/lane.&lt;/P&gt;&lt;P&gt;If we increase the CSI camera clock from 395MHz to 400MHz to support 800Mbps/lane, we are getting distorted frames.&lt;/P&gt;&lt;P&gt;So we wanted to know that really we can achieve the mentioned data rate for 4 lanes or its just based on theoritical calculation.&lt;/P&gt;&lt;P&gt;Thanks for your support.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Oct 2017 10:41:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723833#M112546</guid>
      <dc:creator>titusstalin</dc:creator>
      <dc:date>2017-10-26T10:41:17Z</dc:date>
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    <item>
      <title>Re: Is it possible to achieve TRM mentioned data rate in MIPI CSI ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723834#M112547</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp; Titus&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;reason may be ipu bandwidth issue, please try with baremetal sdk (or remove other drivers/applications&lt;/P&gt;&lt;P&gt;from test).&lt;/P&gt;&lt;P&gt;Github SDK&lt;BR /&gt;&lt;A href="https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK"&gt;https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Right, mentioned data rate is based on theoritical calculation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Oct 2017 23:13:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723834#M112547</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-10-26T23:13:24Z</dc:date>
    </item>
    <item>
      <title>Re: Is it possible to achieve TRM mentioned data rate in MIPI CSI ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723835#M112548</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Igor.&lt;/P&gt;&lt;P&gt;Actually I can't use this SDK since its very old and our nitrogen specific board support code will not be available.&lt;/P&gt;&lt;P&gt;And also could you please check the data rate with your customers who using 4 lanes for their camera ?&lt;/P&gt;&lt;P&gt;Any other method to verify this ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your help!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Oct 2017 12:48:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723835#M112548</guid>
      <dc:creator>titusstalin</dc:creator>
      <dc:date>2017-10-27T12:48:29Z</dc:date>
    </item>
    <item>
      <title>Re: Is it possible to achieve TRM mentioned data rate in MIPI CSI ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723836#M112549</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/titusstalin"&gt;titusstalin&lt;/A&gt;‌ :&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Did you have find out how to achieve the mentioned data rate of 800Mbps with 4-lanes?&lt;/P&gt;&lt;P&gt;I found mipi-csi2-rx maybe could not support up to 800Mbps with 4-lanes.&lt;/P&gt;&lt;P&gt;Best Regard.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Aug 2020 06:50:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-it-possible-to-achieve-TRM-mentioned-data-rate-in-MIPI-CSI/m-p/723836#M112549</guid>
      <dc:creator>eason-tang</dc:creator>
      <dc:date>2020-08-21T06:50:13Z</dc:date>
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