i.MX ProcessorsのトピックRe: ATDTW bit of USB Command Register

ATDTW bit of USB Command Register

AtomuHidaka — Sun, 09 Dec 2012 23:22:40 GMT

At USB OTG HOST1 Contoller (Device Mode) of Reference Manual 56.6.18 describes ATDTW (Add dTD TripWire - Read/Write) bit of USB Command Register (USB_USBCMD) is bit-12, at Page 3304. But the source code of linux arcotg and RM of i.MX53 describes it as bit-14.

Which is correct?

Re: ATDTW bit of USB Command Register

Yuri — Wed, 12 Dec 2012 03:13:36 GMT

Taking into account that USB modules for devices of i.MX series are very similar and are based on the same IP,
it is reasonable to guess that there are misprints in the i.MX50 RM regarding USB Command Register (USB_USBCMD)
in section 56.6.18. Correct description may be found in i.MX53 / 28 / 6 RM(s). I will report about misprints to the doc
team. Thank for this information !

Re: ATDTW bit of USB Command Register

AtomuHidaka — Wed, 12 Dec 2012 08:13:47 GMT

Hi Yuri,
Thank you for your response. It was very helpful advice. I will refer i.MX53 RM.

Regarding misprints of i.MX50 RM, I have found another following misprints at 56.6.30 Port Status and Control (USB_PORTSC), page 3323.
- The bit map chart is incorrect.
- Bit 28, PTW bit assignment should be 0 and 1. Those are not 1 and 2.

Please send these informations to the doc team, too.

Re: ATDTW bit of USB Command Register

Yuri — Wed, 12 Dec 2012 08:31:58 GMT

I've already reported about the USB_PORTSC to the doc team earlier.

The table “USB_PORTSC field descriptions” is correct, but on the figure the bits

on right side from PFSC in the illustration should be shifted right (1 bit).

Writing PTW bit as 0 selects the 8-bit [60MHz] UTMI interface.

Writing PTW bit as 1 selects the 16-bit [30MHz] UTMI interface.

Re: ATDTW bit of USB Command Register

AtomuHidaka — Wed, 12 Dec 2012 09:07:48 GMT

Yuri,

OK, Thank you for your notice.