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    <title>i.MX ProcessorsのトピックRe: why is this difference in memory Mapped and port mapped interafcing</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/why-is-this-difference-in-memory-Mapped-and-port-mapped/m-p/721050#M112104</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Aditya&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this depends in internal processor architecture, as memory and port may&lt;/P&gt;&lt;P&gt;use different internal processor buses. Please check processor manual with&lt;/P&gt;&lt;P&gt;description of internal mapping of peripherals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 25 Oct 2017 23:01:13 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-10-25T23:01:13Z</dc:date>
    <item>
      <title>why is this difference in memory Mapped and port mapped interafcing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/why-is-this-difference-in-memory-Mapped-and-port-mapped/m-p/721049#M112103</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the memory mapped I/O interfacing , peripherals are connected/interfaced over the address bus. If there are 32 address lines , then theoretically we can interface 2 power 32 devices to the CPU. This interfacing also includes MEMR&amp;nbsp; and MEMW (Memory Read and Memory write signals).&lt;/P&gt;&lt;P&gt;In the Port Mapped I/O interfacing , peripherals are again connected to the same address lines . Just the instructions for reading and writing would be different like inportb&amp;nbsp; and outportb&amp;nbsp; and the control signals would be IOR and IOW (IO READ and IO WRITE) . But the number of devices which can be interfaced will probably be less i.e. 2 power 16 .&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why is this difference between Memory Mapped I/O and Port Mapped I/O.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Aditya Nagal&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Oct 2017 13:45:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/why-is-this-difference-in-memory-Mapped-and-port-mapped/m-p/721049#M112103</guid>
      <dc:creator>adityanagal</dc:creator>
      <dc:date>2017-10-25T13:45:45Z</dc:date>
    </item>
    <item>
      <title>Re: why is this difference in memory Mapped and port mapped interafcing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/why-is-this-difference-in-memory-Mapped-and-port-mapped/m-p/721050#M112104</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Aditya&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this depends in internal processor architecture, as memory and port may&lt;/P&gt;&lt;P&gt;use different internal processor buses. Please check processor manual with&lt;/P&gt;&lt;P&gt;description of internal mapping of peripherals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Oct 2017 23:01:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/why-is-this-difference-in-memory-Mapped-and-port-mapped/m-p/721050#M112104</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-10-25T23:01:13Z</dc:date>
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