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    <title>topic Re: PCI-E Loopback Mode in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720450#M112017</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have enabled the Loopback_Enable bit and did not get the same signal on both Tx and Rx lanes. The data is sent from a FPGA to the iMX6 processor (Tx lane of FPGA to Rx lane of processor) and I probed on Tx lane of processor using oscilloscope. I expect to get the same signal on both lanes.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I further read bit[54] (&lt;SPAN class=""&gt;mac_phy_txdetectrx_loop PIPE receiver detect/loopback request&lt;/SPAN&gt;) of DEBUG 1 (&lt;SPAN class=""&gt;PCIE_PL_DEBUG1&lt;/SPAN&gt;) register and this bit is '0'. Does this mean that the PHY did not get loopback request? Please advice, thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 08 Feb 2018 08:52:48 GMT</pubDate>
    <dc:creator>harrytan</dc:creator>
    <dc:date>2018-02-08T08:52:48Z</dc:date>
    <item>
      <title>PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720448#M112015</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using iMX6 Solo processor and I want to have signal sent out through PCI-E Tx lane get loopback to the Rx lane. This means that Tx and Rx lanes should have the same signal. Is this done by setting the bit 2 (Loopback_Enable) of Port Link Control Register (PCIE_PL_PLCR)? Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/69i4B5893BC156A6481/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Feb 2018 09:29:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720448#M112015</guid>
      <dc:creator>harrytan</dc:creator>
      <dc:date>2018-02-06T09:29:09Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720449#M112016</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Harry&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes this bit is used as part of Local PIPE Loopback procedure usually used&lt;/P&gt;&lt;P&gt;during production test. NXP software BSPs do not use this procedure.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Feb 2018 02:33:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720449#M112016</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-02-07T02:33:01Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720450#M112017</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have enabled the Loopback_Enable bit and did not get the same signal on both Tx and Rx lanes. The data is sent from a FPGA to the iMX6 processor (Tx lane of FPGA to Rx lane of processor) and I probed on Tx lane of processor using oscilloscope. I expect to get the same signal on both lanes.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I further read bit[54] (&lt;SPAN class=""&gt;mac_phy_txdetectrx_loop PIPE receiver detect/loopback request&lt;/SPAN&gt;) of DEBUG 1 (&lt;SPAN class=""&gt;PCIE_PL_DEBUG1&lt;/SPAN&gt;) register and this bit is '0'. Does this mean that the PHY did not get loopback request? Please advice, thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Feb 2018 08:52:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720450#M112017</guid>
      <dc:creator>harrytan</dc:creator>
      <dc:date>2018-02-08T08:52:48Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720451#M112018</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you have any thought on this? Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Harry&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Feb 2018 06:43:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720451#M112018</guid>
      <dc:creator>harrytan</dc:creator>
      <dc:date>2018-02-12T06:43:13Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720452#M112019</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Harry&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look at IP vendor documentation&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_pci_express_dm" title="https://www.synopsys.com/dw/ipdir.php?ds=dwc_pci_express_dm"&gt;DesignWare Dual Mode Controller IP for PCI Express&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Feb 2018 10:04:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/720452#M112019</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-02-12T10:04:07Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/1769087#M216890</link>
      <description>&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;I am also trying to enable the loopback of bit 2. I am using LX208A&amp;nbsp; and I need to enable it by using code warrior in PBL mode.&lt;BR /&gt;could you please explain the detailed procedure that how you have enabled the loopback from starting onward?&lt;/P&gt;</description>
      <pubDate>Tue, 05 Dec 2023 14:11:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/1769087#M216890</guid>
      <dc:creator>Pavan_chate</dc:creator>
      <dc:date>2023-12-05T14:11:42Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Loopback Mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/1772821#M217197</link>
      <description>&lt;P&gt;Hi harrytan,&lt;/P&gt;&lt;P&gt;could you please explain here the procedure how you did enable the loopback and all using code warrior? I need to check the loopback in PBL mode using code warrior.&lt;BR /&gt;&lt;BR /&gt;Thanks and regards,&lt;/P&gt;&lt;P&gt;Pavan&lt;/P&gt;</description>
      <pubDate>Tue, 12 Dec 2023 06:30:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCI-E-Loopback-Mode/m-p/1772821#M217197</guid>
      <dc:creator>Pavan_chate</dc:creator>
      <dc:date>2023-12-12T06:30:36Z</dc:date>
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