i.MX ProcessorsのトピックRe: iMX7D reset issues

iMX7D reset issues

raimarsandner — Thu, 01 Mar 2018 09:31:40 GMT

We have an iMX7D rev1.3 (part number MCIMX7D5EVM10SD) with DDR3L, PMIC is a PF3000 (MC34PF3000A1). U-Boot version is v2016.05. We are experiencing a very inconsistent reset behavior, different from device to device. Test case is "reset" from the u-boot prompt.

Some devices reset fine every time (u_boot_working_reset.txt)
Some devices hang on reset after printing "resetting ..." (u_boot_hanging_reset.txt)
On one device the first reset always works, but it will eventually hang on the second, third or fourth reset.

There is an errata (e10574) with three alternative options to reset the SoC.

Option: "Hardware implementation of power-on-reset (POR) Use the pin muxing capability to route the desired WDOG_B signal to an external signal. That external signal must then be connected at the board level to an active-low power-on control (PWRON) of the PMIC."
Unfortunately we cannot use this option at this point, we have to find a software solution.
Option: "Use SRC_A7RCR0[A7_CORE_POR_RESET0] to reset the ARM A7."
We implemented this option with a u-boot patch (resetmodes.patch) in drivers/watchdog/imx_watchdog.c, reset_cpu.
```
#define SRC_A7RCR0    0x004
#define CORE_POR_RESET0    (1 << 0)
    printf("errata option 2\n");
    setbits_le32((SRC_BASE_ADDR + SRC_A7RCR0), CORE_POR_RESET0);
```
This option fails on all devices, system hangs after "resetting ..."

Option: "Use the SNVS LPCR register to turn off the system power"

#define SNVS_LPCR    0x38
#define LPCR_DUMP_EN    (1 << 5)
#define LPCR_TOP    (1 << 6)
    printf("errata option 3\n");
    setbits_le32((SNVS_BASE_ADDR + SNVS_LPCR), LPCR_DUMP_EN);
    setbits_le32((SNVS_BASE_ADDR + SNVS_LPCR), LPCR_TOP);

This does not reset the chip.

Any help to get a consistent SoC reset is very much appreciated. Why don't the reset options work as described in the errata?

Update: Does SNVS_PMIC_ON_REQ have to be connected to the PMIC PWRON pin for Option 3 to work correctly? This is not the case in our layout.

Thank you!

Re: iMX7D reset issues

wad1 — Thu, 01 Mar 2018 18:52:57 GMT

It sounds like you have run into the same problem we saw (although we were using the PF3001).

Basically, we discovered that external circuitry is needed with the iMX7 to ensure reliable reset/watchdog. They pointed us at the same errata, but after we had developed a external work-around, so we never tried the options listed in the errata.

How to enable watchdog on iMX7

Re: iMX7D reset issues

igorpadykov — Thu, 01 Mar 2018 23:13:00 GMT

Hi Raimar

yes, PMIC_ON_REQ have to be connected to the PMIC PWRON as it is done on i.MX7D Sabre SD board

Schematics (2)
Design files for i.MX 7Dual (REV D)
Design files, including hardware schematics, Gerbers, and OrCAD files for i.MX 7Dual (REV D)
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?fpsp=1&tab=Design_Tools_Tab

Also seems Option 3 implements patch described on

Q&A: How is mx6 PMIC_ON_REQ under SW control?

Reason is that soft reset (WARM, like wdog_rst_b) does not reset chip test logic
(sjc, iomuxc, dap) and just puts sdram in self_refresh.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: iMX7D reset issues

raimarsandner — Fri, 02 Mar 2018 09:31:04 GMT

Hi Igor,

thanks for the reply. We have the PMIC PWRON hard-wired to VSNVS by a 100k pull-up. We need a software solution until a hardware redesign (which takes considerable time) can fix this situation.

So it seems option 1 and option 3 are not available to us due to our current board layout. A few questions remain:

How about option 2? Our implementation just hangs after setting SRC_A7RCR0[A7_CORE_POR_RESET0], is there a chance to make this work?
Can we use the I2C interface of the PMIC to trigger a reset? Any hack is welcome if it does the job of resetting the PMIC (e.g. fault mode, programmatically invert PWRON bit, whatever it takes). I did not find anything in the reference manual, but who knows...
What can be the reason that some devices reset without problems and others do not?

Re: iMX7D reset issues

igorpadykov — Fri, 02 Mar 2018 11:46:55 GMT

Hi Raimar

for option2 you can debug, for example check if reset is present on ddr3.

However performing only processor internal por (with A7_CORE_POR_RESET0) may be insufficient, as for

example on i.MX7D Sabre SD schematic external POR resets not only processor

but also external power supply 3V3 PERI, so resetting whole board: processor + all peripheral chips.

I am afraid there is no way for I2C interface of the PMIC to trigger a reset.

Best regards
igor