<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic i.mx6SX ENET RGMII connection in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6SX-ENET-RGMII-connection/m-p/716888#M111386</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The i.mx6SX has a register called&amp;nbsp;ENETx_ECR_RXC_DLY &amp;amp;&amp;nbsp;&lt;SPAN&gt;ENETx_ECR_TXC_DLY. There is no explanation on what type (lenght) of delay it enables. Where can I find a detailed description?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The background is that I need to connect i.mx6SX RGMII port to a switch. That typically needs a tuned delay for the Tx &amp;amp; Rx clock's. Normally that delay is programmable on the PHY side. But since this is not connected to a PHY I need to manage the the clock delay. The mentioned register values might be able to do that but it's impossible to determine upfront if I don't know what they do exactly.&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 05 Feb 2018 15:35:05 GMT</pubDate>
    <dc:creator>DavorBogavac</dc:creator>
    <dc:date>2018-02-05T15:35:05Z</dc:date>
    <item>
      <title>i.mx6SX ENET RGMII connection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6SX-ENET-RGMII-connection/m-p/716888#M111386</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The i.mx6SX has a register called&amp;nbsp;ENETx_ECR_RXC_DLY &amp;amp;&amp;nbsp;&lt;SPAN&gt;ENETx_ECR_TXC_DLY. There is no explanation on what type (lenght) of delay it enables. Where can I find a detailed description?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The background is that I need to connect i.mx6SX RGMII port to a switch. That typically needs a tuned delay for the Tx &amp;amp; Rx clock's. Normally that delay is programmable on the PHY side. But since this is not connected to a PHY I need to manage the the clock delay. The mentioned register values might be able to do that but it's impossible to determine upfront if I don't know what they do exactly.&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 05 Feb 2018 15:35:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6SX-ENET-RGMII-connection/m-p/716888#M111386</guid>
      <dc:creator>DavorBogavac</dc:creator>
      <dc:date>2018-02-05T15:35:05Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6SX ENET RGMII connection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6SX-ENET-RGMII-connection/m-p/716889#M111387</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Davor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/435696"&gt;ENETx_ECR settings in i.MX6SoloX&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 05 Feb 2018 23:19:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6SX-ENET-RGMII-connection/m-p/716889#M111387</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-02-05T23:19:57Z</dc:date>
    </item>
  </channel>
</rss>

