topic Re: IMX6S power-up sequence in i.MX Processors

IMX6S power-up sequence

wayne_1 — Tue, 24 Oct 2017 11:47:54 GMT

Hi all,

in our design VDDHIGH_IN and VDD_SNVS_IN of IMX6 Solo are supplied by VGEN4 of PMIC MMPF0100 (NP). VGEN4 (3V0) is supplied by PMIC SW2 (3V3) and this 3V3 is also supplying IMX6 GPIO voltages (NVCC_xxx). VGEN4 and SW2 are programmed to be the first in power-up sequence. Any problem here?

Many thanks!

Re: IMX6S power-up sequence

igorpadykov — Wed, 25 Oct 2017 00:21:55 GMT

Hi wayne_1

according to datasheet VDDHIGH_IN and VDD_SNVS_IN should be powered first,
in suggested sequence it will be second, as 3V3 is also supplying IMX6 GPIO voltages (NVCC_xxx).

Best regards
igor
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Re: IMX6S power-up sequence

wayne_1 — Wed, 25 Oct 2017 05:51:12 GMT

Thanks Igor,

so if VDD_SNVS_IN is connected together with VDDHIGH_IN they still need to be clearly first in sequence?

Now VDD_SNVS_IN + VDDHIGH_IN start up together with 3V3. What is the actual risk here?

We don't have coin cell connected in VDD_SNVS_IN.

Best regards,

Wayne