i.MX7 ENET receive initialization?

sebastianhuber — Tue, 26 Sep 2017 12:26:27 GMT

Hello,

I try to port the Ethernet interface driver from FreeBSD for i.MX6 to an i.MX7 Dual. The driver works in the loop back mode RCR[LOOP] == 1. I can also transmit frames. The problem is on the receiver side in normal mode (RCR[LOOP] == 0). The legacy descriptor ring is set up properly:

Once I start the receive DMA with RDAR <- (1 << 24) and send one ARP request to the target (frame length < 0x600), I get this:

_address|________0________4________8________C
801FFB80| 00800600 9FE54010 80000000 9FE54810
801FFB90| 80000000 9FE53010 80000000 9FE58810
801FFBA0| 80000000 9FE57010 80000000 9FE57810

Only the first 16 bytes of the frame show up in the buffer:

_address|_0__1__2__3__4__5__6__7_
9FE54010| FF FF FF FF FF FF 68 05
9FE54018| CA 3C 5A 26 08 06 00 01
9FE54020| 00 00 00 00 00 00 00 00
9FE54028| 00 00 00 00 00 00 00 00
9FE54030| 00 00 00 00 00 00 00 00
9FE54038| 00 00 00 00 00 00 00 00
9FE54040| 00 00 00 00 00 00 00 00
9FE54048| 00 00 00 00 00 00 00 00
9FE54050| 00 00 00 00 00 00 00 00
9FE54058| 00 00 00 00 00 00 00 00
9FE54060| 00 00 00 00 00 00 00 00
9FE54068| 00 00 00 00 00 00 00 00
9FE54070| 00 00 00 00 00 00 00 00
9FE54078| 00 00 00 00 00 00 00 00
9FE54080| 00 00 00 00 00 00 00 00
9FE54088| 00 00 00 00 00 00 00 00
9FE54090| 00 00 00 00 00 00 00 00
9FE54098| 00 00 00 00 00 00 00 00
9FE540A0| 00 00 00 00 00 00 00 00
9FE540A8| 00 00 00 00 00 00 00 00
9FE540B0| 00 00 00 00 00 00 00 00
9FE540B8| 00 00 00 00 00 00 00 00
9FE540C0| 00 00 00 00 00 00 00 00
9FE540C8| 00 00 00 00 00 00 00 00
9FE540D0| 00 00 00 00 00 00 00 00

The BC flag (broadcast) is set correctly in the BD status. However, the length is set to 0x600 (this is MRBR), the L flag is not set and the receive seems to be stopped. I see this behaviour on two different boards. U-Boot and Linux works with Ethernet without problems.

The Ethernet registers are initialized as follows:

EIR 05800000
EIMR 0A400000
RDAR 01000000
TDAR 00000000
ECR 70000122
MMFR 602A3800
MSCR 0000001A
MIBC 40000000
RCR 05EE0064
TCR 00000004
PALR 00D0933D
PAUR EAED8808
OPD 00010020
TXIC0 00000000
TXIC1 00000000
TXIC2 00000000
RXIC0 00000000
RXIC1 00000000
RXIC2 00000000
IAUR 00000000
IALR 00000000
GAUR 00000100
GALR 00800000
TFWR 00000102
RDSR1 00000000
TDSR1 00000000
MRBR1 00000000
RDSR2 00000000
TDSR2 00000000
MRBR2 00000000
RDSR 801FFB80
TDSR 801FFD00
MRBR 00000600
RSFL 00000000
RSEM 00000000
RAEM 00000004
RAFL 00000004
TSEM 00000000
TAEM 00000004
TAFL 00000008
TIPG 0000000C
FTRL 000007FF
TACC 00000000
RACC 00000000
RCMR1 00000000
RCMR2 00000000
DMA1CFG 00000000
DMA2CFG 00000000
RDAR1 00000000
TDAR1 00000000
RDAR2 00000000
TDAR2 00000000
QOS 00000000
ATCR 00000000
ATVR 00000000
ATOFF 00000000
ATPER 3B9ACA00
ATCOR 00000000
ATINC 00000000
ATSTMP XXXXXXXX
TGSR 00000000
TCSR0 00000000
TCCR0 00000000
TCSR1 00000000
TCCR1 00000000
TCSR2 00000000
TCCR2 00000000
TCSR3 00000000
TCCR3 00000000

Re: i.MX7 ENET receive initialization?

igorpadykov — Tue, 26 Sep 2017 23:23:00 GMT

Hi Sebastian

for i.MX7 ENET initialization one can look at uboot

uboot-imx.git - Freescale i.MX u-boot Tree

or linux enet driver described in Chapter 44 ENET IEEE-1588 Driver

attached Linux Manual.

linux-imx.git - i.MX Linux Kernel

Best regards
igor
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Re: i.MX7 ENET receive initialization?

sebastianhuber — Wed, 27 Sep 2017 06:28:09 GMT

Thanks for the hints. I found the problem. The i.MX7D needs a 64 byte receive buffer alignment in contrast to the 16 byte alignment required by previous FEC versions. It is a bit strange that the loop back mode works even in case the alignment requirements are not met.

i.MX Processorsのトピックi.MX7 ENET receive initialization?

i.MX7 ENET receive initialization?

Re: i.MX7 ENET receive initialization?

Re: i.MX7 ENET receive initialization?