i.MX Processors中的主题 Re: PCIE PLL lock time out on IMX7D?

PCIE PLL lock time out on IMX7D?

benjaminblanton — Thu, 21 Sep 2017 23:01:01 GMT

Hi we are running the PCIE clock of the internal PLL and during boot we receive an error that the PCIE PLL lock has timed out. Both the 1.0V and 1.8V supplies have power. Is there something else to look for?

Re: PCIE PLL lock time out on IMX7D?

Yuri — Fri, 22 Sep 2017 07:23:10 GMT

Hello,

hope the following helps.

https://community.nxp.com/message/918627

Have a great day,
Yuri

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Re: PCIE PLL lock time out on IMX7D?

benjaminblanton — Mon, 25 Sep 2017 21:01:42 GMT

We tried this and it has not resolved the issue.

Re: PCIE PLL lock time out on IMX7D?

benjaminblanton — Tue, 26 Sep 2017 20:21:31 GMT

Also to be clear, can the PCIe phy be run without an external clock on PCIE_REFCLKIN_P/N and only using the internal oscillator? Also is PCIE_REFCLKIN_P/N LVDS or HCSL compatible?

Re: PCIE PLL lock time out on IMX7D?

Yuri — Wed, 27 Sep 2017 08:58:41 GMT

Hello,

You may look at "PCIe® Certification Guide for i.MX 7Dual", where we can see,

that the PCIE clock can be generated by the chip; no external clock is required.

https://www.nxp.com/docs/en/user-guide/PCIECGFIMX7DUG.pdf

Regards,

Yuri.

Re: PCIE PLL lock time out on IMX7D?

benjaminblanton — Wed, 27 Sep 2017 18:08:11 GMT

Testing on the MCIMX7D-SABRE board, if we remove the 0R R632 and R633, disconnecting the external oscillator from PCIE_REFCLKIN_N/P, what registers do we need to set to obtain a PLL lock of the internal oscillator for the PCI Phy?

Thanks

Re: PCIE PLL lock time out on IMX7D?

fabio_estevam — Wed, 27 Sep 2017 22:03:17 GMT

Hi Benjamin,

Are you able to get PCI working in Linux?

I don't see PCI support in U-Boot for mx7dsabresd.

Re: PCIE PLL lock time out on IMX7D?

benjaminblanton — Wed, 27 Sep 2017 22:12:32 GMT

On the Sabre board we can lock the PCI Phy PLL using the external oscillator on the board, but if remove the 0 Ohm resistors to mimic our board and attempt to set the Phy to the internal 100 MHz we get same "unable to sync pll" error we see on our board. Figure 11-52 shown below suggests the PLL is only connected to the PCIE_REFCLKIN and that an external oscillator/clock IS required.

Thoughts?

Re: PCIE PLL lock time out on IMX7D?

benjaminblanton — Mon, 02 Oct 2017 17:36:59 GMT

Any thoughts on this?

Re: PCIE PLL lock time out on IMX7D?

Yuri — Wed, 18 Oct 2017 06:24:08 GMT

Hello,

The current i.MX7 Datasheet contains misprints regarding PCIe PHY reference

clock requirements:

1. The min value of VMAX (33) and the min value of VMIN (400) should be removed.

2. The max value of VCROSS should be 550mV.

So, our PCIe PHY reference clock requirements is - at least - very close to HCSL.

Regards,

Yuri.