winbond qspi boot question

qiangdaemon — Thu, 24 Aug 2017 12:31:04 GMT

My board is iMX6UL EVK。
We can use the onboard QSPI NOR flash(N25Q256A) to boot up linux。
We found 3 config files for 3 NOR flash under MFG tool files。
qspi-nor-macronix-mx25l51245g-config
qspi-nor-micron-n25q256a-config
qspi-nor-spansion-s25fl128s-config
We need to make qspi-nor-winbond-w25q128bv-config .Mainly to modify the LUT part。
And now we need to use another QSPI NOR flash(W25Q128BV/W25Q256) to bringup the system。

My soft environment:"yocto 4.1.15-1.0.0"
Mfgtool:"L4.1.15-1.0.0_ga-mfg-tools"
I found a reference doc "MX6UL_Development_qspi-norflash-boot.doc"
I add qspi-nor-winbond-w25q128bv-config ,modify kernel-mfgtool-source,modify uboot-source code.You can view the patch kernel and uboot attachment。but it didnot boot?

There are two question,I confuse about qspi-nor-macronix-mx25l51245g-config and qspi-nor-micron-n25q256a-config different
(1)what different w25q128fv and w25q256 ?
(2)w25q128fv is 1xdie? and w25q256 is 2xdie?
This is qspi-nor-winbond-w25q128-config
0 /*dqs_loopback=0 or 1*/
0 /*hold_delay=0 to 3*/
0 /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0 /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/
1 /*device_quad_mode_en=1 to enable sending command to SPI device*/
2 /*device_cmd=command to device for enableing Quad I/O mode*/
3000002 /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
2000000 /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
3 /*cs_hold_time=0 to 0xF*/
3 /*cs_setup_time=0 to 0xF*/
8000000 /*sflash_A1_size=size in byte(hex)*/
0 /*sflash_A2_size=size in byte(hex)*/
0 /*sflash_B1_size=size in byte(hex)*/
0 /*sflash_B2_size=size in byte(hex)*/
1 /*sclk_freq=0 to 6*/
0 /*busy_bit_offset=bit position of device BUSY in device status register*/
4 /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
0 /*sflash_port=0 or 1 (Port B used)*/
0 /*ddr_mode_enable=0 or 1*/
0 /*dqs_enable=0 or 1*/
0 /*parallel_mode_enable=0 or 1*/
0 /*portA_cs1=0 or 1*/
0 /*portB_cs1=0 or 1*/
0 /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0 /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
0 /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
0a18046b /*lut[0] command sequence*/
0e081201 /*lut[1] command sequence*/
24001e04 /*lut[2] command sequence*/
0 /*lut[3] command sequence*/
1c010405 /*lut[4] command sequence*/
2400 /*lut[5] command sequence*/
0 /*lut[6] command sequence*/
0 /*lut[7] command sequence*/
24000406 /*lut[8] command sequence*/
0 /*lut[9] command sequence*/
0 /*lut[10] command sequence*/
0 /*lut[11] command sequence*/
20010431 /*lut[12] command sequence*/
2400 /*lut[13] command sequence*/
0 /*lut[14] command sequence*/
0 /*lut[15] command sequence*/
1c010435 /*lut[16] command sequence*/
2400 /*lut[17] command sequence*/
0 /*lut[18] command sequence*/
0 /*lut[19] command sequence*/
0 /*lut[20] command sequence*/
0 /*lut[21] command sequence*/
0 /*lut[22] command sequence*/
0 /*lut[23] command sequence*/
0 /*lut[24] command sequence*/
0 /*lut[25] command sequence*/
0 /*lut[26] command sequence*/
0 /*lut[27] command sequence*/
0 /*lut[28] command sequence*/
0 /*lut[29] command sequence*/
0 /*lut[30] command sequence*/
0 /*lut[31] command sequence*/
0 /*lut[32] command sequence*/
0 /*lut[33] command sequence*/
0 /*lut[34] command sequence*/
0 /*lut[35] command sequence*/
0 /*lut[36] command sequence*/
0 /*lut[37] command sequence*/
0 /*lut[38] command sequence*/
0 /*lut[39] command sequence*/
0 /*lut[40] command sequence*/
0 /*lut[41] command sequence*/
0 /*lut[42] command sequence*/
0 /*lut[43] command sequence*/
0 /*lut[44] command sequence*/
0 /*lut[45] command sequence*/
0 /*lut[46] command sequence*/
0 /*lut[47] command sequence*/
0 /*lut[48] command sequence*/
0 /*lut[49] command sequence*/
0 /*lut[50] command sequence*/
0 /*lut[51] command sequence*/
0 /*lut[52] command sequence*/
0 /*lut[53] command sequence*/
0 /*lut[54] command sequence*/
0 /*lut[55] command sequence*/
0 /*lut[56] command sequence*/
0 /*lut[57] command sequence*/
0 /*lut[58] command sequence*/
0 /*lut[59] command sequence*/
0 /*lut[60] command sequence*/
0 /*lut[61] command sequence*/
0 /*lut[62] command sequence*/
0 /*lut[63] command sequence*/
0 /*default:1000001 read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/
0 /*enable_dqs_phase=0 or 1*/
0 /*config_cmds_en, enable config command*/
0 /*config_cmds[0]*/
0 /*config_cmds[1]*/
0 /*config_cmds[2]*/
0 /*config_cmds[3]*/
0 /*config_cmds_args[0]*/
0 /*config_cmds_args[1]*/
0 /*config_cmds_args[2]*/
0 /*config_cmds_args[3]*/
0 /*io_pad_override_setting QSPI pins override setting*/
0 /*reserve[0], 25 byte reserved area*/
0 /*reserve[1], 25 byte reserved area*/
0 /*reserve[2], 25 byte reserved area*/
0 /*reserve[3], 25 byte reserved area*/
0 /*reserve[4], 25 byte reserved area*/
0 /*reserve[5], 25 byte reserved area*/
0 /*reserve[6], 25 byte reserved area*/
0 /*reserve[7], 25 byte reserved area*/
0 /*reserve[8], 25 byte reserved area*/
0 /*reserve[9], 25 byte reserved area*/
0 /*reserve[10], 25 byte reserved area*/
0 /*reserve[11], 25 byte reserved area*/
0 /*reserve[12], 25 byte reserved area*/
0 /*reserve[13], 25 byte reserved area*/
0 /*reserve[14], 25 byte reserved area*/
0 /*reserve[15], 25 byte reserved area*/
0 /*reserve[16], 25 byte reserved area*/
0 /*reserve[17], 25 byte reserved area*/
0 /*reserve[18], 25 byte reserved area*/
0 /*reserve[19], 25 byte reserved area*/
0 /*reserve[20], 25 byte reserved area*/
0 /*reserve[21], 25 byte reserved area*/
0 /*reserve[22], 25 byte reserved area*/
0 /*reserve[23], 25 byte reserved area*/
0 /*reserve[24], 25 byte reserved area*/
c0ffee01 /*tag, QSPI configuration tag, should be 0xc0ffee01*/

There bringup uboot and qspi-header log attachment.
Best Regards
Daemon

Original Attachment has been moved to: imx6ulevk_w25q256-new.log.zip

Original Attachment has been moved to: imx6ulevk_n25q256.log.zip

Original Attachment has been moved to: w25q128.txt.zip

Original Attachment has been moved to: qspi-nor-winbond-w25q128-config.zip

Re: winbond qspi boot question

jimmychan — Tue, 05 Sep 2017 02:39:37 GMT

According to the w25q128bv datasheet, Write status register is 01H, it write two bytes S7-S0 and S15-S8.

And there is no instruction code 31h in w25q128bv, so please try to change the CMD "Write register (sequence 3)" to 01.

20010431 /*lut[12] command sequence*/ <-- 20010401

2400   /*lut[13] command sequence*/
0   /*lut[14] command sequence*/
0   /*lut[15] command sequence*/

The purpose is to set the QE bit to 1. The QE bit is in S15-S8. The device_cmd is 2.

If still not work, please try to set the device_cmd to 0202. It should be set the Write enable and QE bit.

Re: winbond qspi boot question

stefanroese — Wed, 19 Feb 2020 11:02:43 GMT

Hi!

We are currently trying to boot from QSPI on an i.MX6ULZ equipped with an Winbond W25Q256J QSPI NOR.And booting does not work, most likely because of the not matching QSPI config header at 0x400. I already tried the config file above, also with the changes suggested by jimmychan, but still it does not work.

So before I dig into this deeper, is there someone who is successfully booting via QSPI from a Winbond chip? If yes, could you please share the config header?

Mandy thanks,

Stefan

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