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    <title>topic Re: Question about CSIx_SENS_PRTCL bit function in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705758#M109653</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your quick response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Progressive mode, I have three additional questions.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In this time,&amp;nbsp; section "2.5.2 CCIR Register Setting for Progressive Signal" in document&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-332679"&gt;iMX6 IPU TVIN Application Notes&lt;/A&gt;&amp;nbsp; say that&amp;nbsp;&lt;/P&gt;&lt;P&gt;"in register IPU_CSI_CCIR_CODE_1, only CSI_STRT_FLD0_BLNK_1ST, CSI_STRT_FLD0_ACTV and&lt;BR /&gt;CSI_END_FLD0_ACTV are used, the three bits register value for each region (MSB to LSB) is H, V, F&lt;BR /&gt;data, and F is always 0."&lt;/P&gt;&lt;P&gt;1) Why only this three bit field are used?&lt;/P&gt;&lt;P&gt;2) Some video decoder output BT656 progressive data with F bit = 1.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; In this time, is this decoder not used with iMX6?&lt;/P&gt;&lt;P&gt;3) How detect a start line of the new frame/ blanking and Active Video area?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Only F,V,H bit pattern match with CSI_CCIR_CODE_1 register bit?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; or use some other condition like IPU_CSI_SENS_FRM_SIZE and&amp;nbsp;IPU_CSI_ACT_FRM_SIZE value.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishii.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 16 Oct 2017 12:19:51 GMT</pubDate>
    <dc:creator>takayuki_ishii</dc:creator>
    <dc:date>2017-10-16T12:19:51Z</dc:date>
    <item>
      <title>Question about CSIx_SENS_PRTCL bit function</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705756#M109651</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question about CSIx_SENS_PRTCL bit setteng, between Interlace and Progressive.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When, CSI set to input BT656 interlace like a section "2.1.1 BT.656 Interlace Setting" in&amp;nbsp;&lt;/P&gt;&lt;P&gt;document&amp;nbsp;i.MX6 IPU TVIN Application Note.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In this time, if CSIx_SENS_PRTCL bit change from&amp;nbsp;0x3(BT.656 interlaced mode)&lt;/P&gt;&lt;P&gt;to&amp;nbsp;0x2(BT.656 progressive mode), it can capture only field 0 line data because only&lt;/P&gt;&lt;P&gt;detect EAV/SAV pattern setting in IPU_CSI_CCIR_CODE_1 register.&lt;/P&gt;&lt;P&gt;And the&amp;nbsp;&lt;SPAN&gt;IPU_CSI_CCIR_CODE_2 register setting is ignored.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is it correct?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Ishii.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Oct 2017 12:59:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705756#M109651</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2017-10-13T12:59:50Z</dc:date>
    </item>
    <item>
      <title>Re: Question about CSIx_SENS_PRTCL bit function</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705757#M109652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Ishii&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes this understanding is correct, on p.5 document states:&lt;/P&gt;&lt;P&gt;"IPU_CSI_CCIR_CODE_1, it is for frame EAV/SAV setting&lt;BR /&gt;IPU_CSI_CCIR_CODE_2, not used for progressive mode "&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Oct 2017 23:05:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705757#M109652</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-10-13T23:05:26Z</dc:date>
    </item>
    <item>
      <title>Re: Question about CSIx_SENS_PRTCL bit function</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705758#M109653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your quick response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Progressive mode, I have three additional questions.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In this time,&amp;nbsp; section "2.5.2 CCIR Register Setting for Progressive Signal" in document&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-332679"&gt;iMX6 IPU TVIN Application Notes&lt;/A&gt;&amp;nbsp; say that&amp;nbsp;&lt;/P&gt;&lt;P&gt;"in register IPU_CSI_CCIR_CODE_1, only CSI_STRT_FLD0_BLNK_1ST, CSI_STRT_FLD0_ACTV and&lt;BR /&gt;CSI_END_FLD0_ACTV are used, the three bits register value for each region (MSB to LSB) is H, V, F&lt;BR /&gt;data, and F is always 0."&lt;/P&gt;&lt;P&gt;1) Why only this three bit field are used?&lt;/P&gt;&lt;P&gt;2) Some video decoder output BT656 progressive data with F bit = 1.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; In this time, is this decoder not used with iMX6?&lt;/P&gt;&lt;P&gt;3) How detect a start line of the new frame/ blanking and Active Video area?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Only F,V,H bit pattern match with CSI_CCIR_CODE_1 register bit?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; or use some other condition like IPU_CSI_SENS_FRM_SIZE and&amp;nbsp;IPU_CSI_ACT_FRM_SIZE value.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishii.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Oct 2017 12:19:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705758#M109653</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2017-10-16T12:19:51Z</dc:date>
    </item>
    <item>
      <title>Re: Question about CSIx_SENS_PRTCL bit function</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705759#M109654</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Ishii&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;for new questions please create new thread.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Oct 2017 12:56:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705759#M109654</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-10-16T12:56:32Z</dc:date>
    </item>
    <item>
      <title>Re: Question about CSIx_SENS_PRTCL bit function</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705760#M109655</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Igor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you very much for your assistance.&lt;/P&gt;&lt;P&gt;I create new thread as following.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/462250"&gt;Question about bt.656 progressive video capture function.&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am looking forward to hearing from you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishii.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Oct 2017 13:49:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-about-CSIx-SENS-PRTCL-bit-function/m-p/705760#M109655</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2017-10-16T13:49:17Z</dc:date>
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