i.MX ProcessorsのトピックRe: i.MX6ULL SDIO interface power up sequence & GPIO sink current

i.MX6ULL SDIO interface power up sequence & GPIO sink current

abin444 — Mon, 21 Aug 2017 13:13:14 GMT

Hi,

We have a couple of questions regarding i.MX6ULL processor we are using in our latest design. Hope you can help us with it.

Can the GPIO pin sink a current of 4mA without damaging the pin?
What is the current sinking capability of i.MX6ULL GPIO pins?
Regarding the power up, the datasheet says the power up sequence to be in the order of:

SNVS
VDD_HIGH
VDD_CORE

But there is no mention about when we can power the interface voltages, say, NVCC_ENET, NVCC_SD1 etc.. we have a different voltage for NVCC_SD1 (1.8V for NVCC_SD1, rest share VDD_HIGH). Where is the interface voltage placed in the power up sequence? Does it mean that we can power them up at any time before the POR is asserted?

4. We now have the VDD_SOC and DDR3L voltages at 1.35V. A single switching regulator (Max current -800mA; Regulator rated for 1A) power both the rails. Are there any problems on sharing the same rail for VDD_SOC & DDR3L?

Thanks & regards

Abin

Re: i.MX6ULL SDIO interface power up sequence & GPIO sink current

igorpadykov — Mon, 21 Aug 2017 23:35:43 GMT

Hi Abin

1. yes

2. sinking capability is not defined, defined only output buffer impedance

provided in sect.4.8.1 Single Voltage GPIO Output Buffer Impedance

i.MX6ULL Datasheet (rev.1.1, 5/2017)
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6ULLCEC.pdf

seems one can estimate it using ibis model (Section "I/O Source and Sink Currents")

http://www.actel.com/documents/Ibis_AN.pdf

3.interface voltages may be powered after VDD_SNVS_IN

4. sharing the same rail for VDD_SOC & DDR3L at 1.35V may have implications

and restrictions on power saving features: for example linux cpu freq driver

changes voltages according to Table 10. Operating Ranges for various cpu

frequencies, also seems Run Mode: LDO Bypassed (used in linux by default)

can not be used with 1.35V

Best regards
igor
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Re: i.MX6ULL SDIO interface power up sequence & GPIO sink current

abin444 — Tue, 22 Aug 2017 17:19:56 GMT

Hello Igor,

Thank you. A few clarifications on 4. Please help me clear it:

4. We intend to use the internal LDOs (means LDOs should not be bypassed). We plan to utilize only those power control features implemented internal to the i.MX6ULL processor hence -no external PMICs.

a) Coming back, I understand that the i.MX6ULL's DVFS feature or the voltage control feature controls only the internal LDO outputs and doesn't affect the external power source and is applicable only when LDOs are enabled (please correct me if I am wrong)- in this case VDD_SOC_IN is 1.35V and is not affected.

b) In that case, isn't it conflicting to say i & ii below

i) sharing the same rail for VDD_SOC & DDR3L at 1.35V may have implications
and restrictions on power saving features:

(How?)

and

ii) for example linux cpu freq driver
changes voltages according to Table 10.

That is only when we run at LDO enabled mode, which is not the default mode, as you said?

for example linux cpu freq driver
changes voltages according to Table 10.

Hope it is optional to enable DVFS if we don't need that level of power saving. I guess it is possible to set a fixed voltage VDD_ARM_CAP & VDD_SOC_CAP- say, 1.1V for both- please confirm.

d) Also I would like to get a clarification on the variable voltage mode.

I guess the variable voltage saves power and the concept applies only to internal LDO voltages and the Run mode should be "LDOs enabled" for it. Please correct me if I am wrong.

Just to make sure we are on the same page:

LDO enabled mode: Requires only 2 external supplies- VDD_HIGH_IN & VDD_SOC_IN. Rest of the required voltages can be generated by configuring internal LDOs from the above two. DVFS enabled in this mode- saves power. VDD_SOC_IN range: 1.25V to 1.5V (we are providing 1.35V, which is within the range). VDD_ARM_CAP & VDD_SOC_CAP mentioned in Table 10 is for internal LDO configuration purpose only. We intend to work in LDO enabled mode.

LDO Bypass mode: No LDOs will be used. entire external voltage will be applied to the load. ie, VDD_SOC_IN reaches at VDD_ARM_CAP & VDD_SOC_CAP. DVFS for power saving not available LDO disabled. VDD_SOC_IN has to be in range: 1.15V to 1.26V.

Re: i.MX6ULL SDIO interface power up sequence & GPIO sink current

igorpadykov — Tue, 22 Aug 2017 23:48:29 GMT

Hi Abin

you are right, there are no restrictions if you are using ldo-on mode.

LDO enabled mode is not linux default mode.

>LDO enabled mode: Requires only 2 external supplies- VDD_HIGH_IN & VDD_SOC_IN.

>Rest of the required voltages can be generated by configuring internal LDOs from the above two.

please look at Figure 40-1. Power system overview i.MX6ULL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf

>I guess the variable voltage saves power and the concept applies only to internal LDO voltages

>and the Run mode should be "LDOs enabled" for it.

lowest power mode is provided by ldo-bypass mode (linux default mode). Processor LDOs are not

used in such case, there is no power loss on them. Voltages are changed externally by pmic, depending on

bus load.

Best regards
igor