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    <title>topic Re: i.MX7 DDR Stress Test Tool in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702382#M109130</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Recent DDR Stress tool provide some calibration for i.MX7 too.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/437875"&gt;https://community.nxp.com/thread/437875&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 15 Sep 2017 03:28:24 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-09-15T03:28:24Z</dc:date>
    <item>
      <title>i.MX7 DDR Stress Test Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702379#M109127</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Experts,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question for DDR Stress Test Tool.&lt;BR /&gt;I use DDR Stress Test Tool Ver 2.70.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;On i.MX6Q, &lt;BR /&gt;After I set the parameters and download the *.inc file, then press the Calibration buttom , if the calibration pass, tool will generate a DDR parameter set to tell me the optimal pararmeter for the testing board. Like:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;MMDC registers updated from calibration&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Write leveling calibration&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00140016&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0024001F&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001B002A&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00150026&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Read DQS Gating calibration&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPDGCTRL0 PHY0 (0x021b083c) = 0x43240338&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPDGCTRL1 PHY0 (0x021b0840) = 0x03240318&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPDGCTRL0 PHY1 (0x021b483c) = 0x43200334&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPDGCTRL1 PHY1 (0x021b4840) = 0x032C0270&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Read calibration&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPRDDLCTL PHY0 (0x021b0848) = 0x3C2E3230&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPRDDLCTL PHY1 (0x021b4848) = 0x38363042&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Write calibration&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPWRDLCTL PHY0 (0x021b0850) = 0x323A3E38&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;MPWRDLCTL PHY1 (0x021b4850) = 0x46304436&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;Success: DDR calibration completed!!!&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;On i.MX7D,&lt;BR /&gt;if calibration pass, the tool just show the "Final write delay = 0xXXXXXXXX" and tell me DDR calibration completed. Linke:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Final write delay = 0x04040404&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;-Note: final delay is based on the center of all passing byte lanes&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Success: DDR calibration completed!!!&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;As my experience, we need to fill the optimal parameters badk into BSP source code.&lt;BR /&gt;However, i.MX7 DDR Stress Test Tool does not generate the optimal parameter&amp;nbsp;set that I can used.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here is my questions:&lt;BR /&gt;1. Does DDR Stress Test Tool generate the optimal DDR parameter on i.MX7 serial?&lt;BR /&gt;2. If "Final write delay" is the optimal parameter, where should I fill back to source code? Which memory address should I fill?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Wayne Kuo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Sep 2017 12:14:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702379#M109127</guid>
      <dc:creator>waynekuo</dc:creator>
      <dc:date>2017-09-13T12:14:47Z</dc:date>
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    <item>
      <title>Re: i.MX7 DDR Stress Test Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702380#M109128</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; According to Stress test FAQ :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;” ... calibration is not supported or needed when using MX7. The reason is, MX7 uses a different memory controller &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;than the MX6 series. The MX6 series memory controller has built-in support for calibration where the MX7 memory &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;controller does not.”&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; Note, i.MX6 DRAM memory controller is MMDC, bit i.MX7 one - is DDRC. Looking over the i.MX7 Reference Manual, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;we can notice, that i.MX7 DDRC supports so called training procedure regarding DQS adjusting : WRITE LEVELING &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;and GATE LEVELING. But there are no considerations about Read Data Bit Delay Calibration and Write Data Bit Delay Calibration.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; The linked below is the recent i.MX6/7 DDR Stress Test Tool V2.70.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A href="https://community.nxp.com/docs/DOC-105652"&gt;i.MX6/7 DDR Stress Test Tool V2.70&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; As for i.MX7D DRAM Register Programming Aid, please refer to the following :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-152468"&gt;i.MX7D DRAM Register Programming Aid&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Please refer to Chapter 1 (Porting U-Boot from an i.MX 6/7 Reference Board to &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;an i.MX 6/7 Custom Board) of “i.MX_BSP_Porting_Guide.pdf” - regarding memory&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;initialization for Linux.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Recent BSP :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A class="link-titled" href="https://www.nxp.com/webapp/Download?colCode=L4.1.15_2.1.0_LINUX_DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType=product" title="https://www.nxp.com/webapp/Download?colCode=L4.1.15_2.1.0_LINUX_DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType=product"&gt;https://www.nxp.com/webapp/Download?colCode=L4.1.15_2.1.0_LINUX_DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageTyp…&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Summary page :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/developer-resources/i.mx-6series-i.mx-7series-software-and-development-tool-resources:IMX_SW" title="https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/developer-resources/i.mx-6series-i.mx-7series-software-and-development-tool-resources:IMX_SW"&gt;i.MX 6 / i.MX 7 Series Software and Development Tool|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, the following may be useful :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;A href="https://community.nxp.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;A class="link-titled" href="http://www.freescale.com/webapp/Download?colCode=FTF-SDS-F0170" title="http://www.freescale.com/webapp/Download?colCode=FTF-SDS-F0170"&gt;http://www.freescale.com/webapp/Download?colCode=FTF-SDS-F0170&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Sep 2017 04:47:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702380#M109128</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-09-14T04:47:41Z</dc:date>
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    <item>
      <title>Re: i.MX7 DDR Stress Test Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702381#M109129</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Yuri,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Here is my understanding, if I'm wrong please correct me.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Cause i.MX6 / i.MX7 DDR controller is different, calibration function on DDR Stress Test Tool is not support for i.MX7 DDR calibration&lt;/SPAN&gt;,but stress test function can still work on i.MX7(?).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;So i.MXX7 DDR calibration step will be:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;1. Fill the i.MX7D DRAM Register Programming Aid and get the DDR register parameters.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;2. Use&amp;nbsp;i.MX6/7 DDR Stress Test Tool to do the stress test for this set of &lt;SPAN&gt;register parameters&lt;/SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;3. Use memtester on OS to do the DDR test.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;If the above step pass, the DDR register parameters are&amp;nbsp;workable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;However, if the parameters generated by&amp;nbsp;&lt;SPAN&gt;i.MX7D DRAM Register Programming Aid can not pass the stress test, what should I do?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Wayne Kuo&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 15 Sep 2017 03:16:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702381#M109129</guid>
      <dc:creator>waynekuo</dc:creator>
      <dc:date>2017-09-15T03:16:45Z</dc:date>
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    <item>
      <title>Re: i.MX7 DDR Stress Test Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702382#M109130</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Recent DDR Stress tool provide some calibration for i.MX7 too.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/437875"&gt;https://community.nxp.com/thread/437875&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 15 Sep 2017 03:28:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702382#M109130</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-09-15T03:28:24Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX7 DDR Stress Test Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702383#M109131</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;just to add some more information:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.&amp;nbsp;&amp;nbsp;The recent version of DDR Stress Tester performs Read and Write calibration. Write leveling calibration&amp;nbsp;is not performed due to the above mentioned reason - different memory controller.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. The DDR Stress Tester then summarizes the results in the following way:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;&lt;EM&gt;Final write delay = 0x04040404&lt;BR /&gt;&lt;/EM&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;-Note: final delay is based on the center of all passing byte lanes&lt;/EM&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Similar&amp;nbsp;output is also for read calibration.Those values should be used to update the DCD table in the source code. The addressses are: 0x30790030&amp;nbsp;- DDR_PHY_OFFSET_WR_CON0&amp;nbsp;(Write Calibration) and 0x30790020 - DDR_PHY_OFFSET_RD_CON0&amp;nbsp;(Read Calibration). You need to look into the DDR PHY registers (DDRP), not DDRC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3. Please use the most recent version of the DDR Stress Tester - v2.70. In the earlier versions there&amp;nbsp;is an issue regarding read/write operations for i.MX7.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Jan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 15 Sep 2017 08:40:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Stress-Test-Tool/m-p/702383#M109131</guid>
      <dc:creator>jan_spurek</dc:creator>
      <dc:date>2017-09-15T08:40:44Z</dc:date>
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