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    <title>i.MX Processors中的主题 Interlace Capturing Modes Via Parallel CSI (IPU1CSI0)</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702148#M109086</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am trying to capture interlace HDMI formats from the ADV7611 Encoder via IPU1CSI0 parallel camera interface. The encoder uses the 16-bit parallel camera bus. I was successfully able to capture 1080p and 720p video formats, but have no luck in capturing 1080i and some other interlace formats.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This encoder also inherits the CSI capturing sensor routines, so for interlace capturing support I switched the sensor data type to :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="background-color: #ffffff; color: #24292e;"&gt; p-&amp;gt;if_type = V4L2_IF_TYPE_BT1120_INTERLACE_SDR;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;And I notice the CSI0 of IPU1 makes the use of &lt;STRONG&gt;CSI-&amp;gt;IC-&amp;gt;MEM&lt;/STRONG&gt; path for capturing in mxc_v4l2_capture.c.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;But I only see the captured frames moving very fast vertically for 1080i input as shown in attached picture. So what else should be in my checklist&amp;nbsp;to get this work from IPU side ? Is there any patches available to make this work ? I am using kernel 4.1.15_1.0 with yocto Krogoth on MX6Q !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;Thanks in Advance&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;Anuradha&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 21 Aug 2017 04:44:59 GMT</pubDate>
    <dc:creator>tengri</dc:creator>
    <dc:date>2017-08-21T04:44:59Z</dc:date>
    <item>
      <title>Interlace Capturing Modes Via Parallel CSI (IPU1CSI0)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702148#M109086</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am trying to capture interlace HDMI formats from the ADV7611 Encoder via IPU1CSI0 parallel camera interface. The encoder uses the 16-bit parallel camera bus. I was successfully able to capture 1080p and 720p video formats, but have no luck in capturing 1080i and some other interlace formats.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This encoder also inherits the CSI capturing sensor routines, so for interlace capturing support I switched the sensor data type to :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="background-color: #ffffff; color: #24292e;"&gt; p-&amp;gt;if_type = V4L2_IF_TYPE_BT1120_INTERLACE_SDR;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;And I notice the CSI0 of IPU1 makes the use of &lt;STRONG&gt;CSI-&amp;gt;IC-&amp;gt;MEM&lt;/STRONG&gt; path for capturing in mxc_v4l2_capture.c.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;But I only see the captured frames moving very fast vertically for 1080i input as shown in attached picture. So what else should be in my checklist&amp;nbsp;to get this work from IPU side ? Is there any patches available to make this work ? I am using kernel 4.1.15_1.0 with yocto Krogoth on MX6Q !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;Thanks in Advance&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #24292e; background-color: #ffffff;"&gt;Anuradha&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 21 Aug 2017 04:44:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702148#M109086</guid>
      <dc:creator>tengri</dc:creator>
      <dc:date>2017-08-21T04:44:59Z</dc:date>
    </item>
    <item>
      <title>Re: Interlace Capturing Modes Via Parallel CSI (IPU1CSI0)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702149#M109087</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I made some improvements in driver side to correct the sizes of the frames it sends to IPU. Now I have 1080i resolution, but the frames move vertically quite faster and I suspect may be CCIR codes are not correct for the interlace mode.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However I can verify that the IPU settings are in accordance with&amp;nbsp;&lt;STRONG&gt;Interlace SDR&amp;nbsp;&lt;/STRONG&gt;specification given in following TVIN application note. Only difference I see is the CCIR code 1-2 and 3 values for the given interlace mode. How should I achieve this ? Can anyone show me an insight to this ?&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-332679"&gt;https://community.nxp.com/docs/DOC-332679&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anuradha&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Aug 2017 04:37:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702149#M109087</guid>
      <dc:creator>tengri</dc:creator>
      <dc:date>2017-08-23T04:37:33Z</dc:date>
    </item>
    <item>
      <title>Re: Interlace Capturing Modes Via Parallel CSI (IPU1CSI0)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702150#M109088</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, I solved the issue by myself, for the INTERLACE_SDR mode, correct CCIR codes&amp;nbsp;have to specified for CODE1 and CODE2 registers with respect to the EAV/SAV codes !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anuradha&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Aug 2017 09:21:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interlace-Capturing-Modes-Via-Parallel-CSI-IPU1CSI0/m-p/702150#M109088</guid>
      <dc:creator>tengri</dc:creator>
      <dc:date>2017-08-23T09:21:01Z</dc:date>
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