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    <title>i.MX ProcessorsのトピックRe: LPDDR2 design guide</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701618#M108979</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your support. I've checked your attached documents.&lt;/P&gt;&lt;P&gt;But, I can not understand clearly to use LPDDR2. Let me confirm again.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hardware Development Guide mentioned DDR routing rules at chapter 3.&lt;/P&gt;&lt;P&gt;Is it able to apply to LPDDR2 design? if no, could you teach me suitable documents to design with LPDDR2?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Oct 2017 01:26:00 GMT</pubDate>
    <dc:creator>Kazuma_Sasaki</dc:creator>
    <dc:date>2017-10-11T01:26:00Z</dc:date>
    <item>
      <title>LPDDR2 design guide</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701616#M108977</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I would like to refer to design rule of LPDDR2. according to following thread. it is described into IMX6DQ6SDLHDG Rev.1.&lt;/P&gt;&lt;P&gt;Where can I get IMX6DQ6SDLHDG Rev.1? If possible, could you re-upload it on this thread?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" class="link-titled" href="https://community.nxp.com/message/511024?commentID=511024#comment-511024" title="https://community.nxp.com/message/511024?commentID=511024#comment-511024"&gt;https://community.nxp.com/message/511024?commentID=511024#comment-511024&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Oct 2017 14:08:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701616#M108977</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2017-10-10T14:08:46Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 design guide</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701617#M108978</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Kazuma&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please refer to attached rev.1 document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Oct 2017 22:59:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701617#M108978</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-10-10T22:59:57Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 design guide</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701618#M108979</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your support. I've checked your attached documents.&lt;/P&gt;&lt;P&gt;But, I can not understand clearly to use LPDDR2. Let me confirm again.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hardware Development Guide mentioned DDR routing rules at chapter 3.&lt;/P&gt;&lt;P&gt;Is it able to apply to LPDDR2 design? if no, could you teach me suitable documents to design with LPDDR2?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Oct 2017 01:26:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-design-guide/m-p/701618#M108979</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2017-10-11T01:26:00Z</dc:date>
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