topic PCIe READ PROBLEM FROM IMX6.SOLOX in i.MX Processors

PCIe READ PROBLEM FROM IMX6.SOLOX

steveretzlaff — Mon, 11 Sep 2017 22:39:18 GMT

Hi, we are trying to maximum performance using an I.MX6 SoloX chip as the PCIe master/RC when reading 32-bit integer data from a gen1 EP based on a directly connected on-board FPGA. Currently we are able to get only 500 K 32-bit words/second from the FPGA FIFO (implemented on BAR0) when reading from software on the ARM, in the Linux kernel.

Because this is a slotless direct connection from the I.MX6 RC to the FPGA EP, there is no opportunity to monitor with a PCIe Analyzer. We can, however, monitor PCIe activity with ChipScope from the FPGA.

Based on measuring the data received on the ARM and the timing of the read requests on the PCIe interface, we are reasonably certain the EP is sending one word (32 bits) per TLP instead of the maximum of 16 (64 bytes). We can’t seem to get read bursting to work using either ioread32() or memcpy() calls from the I.MX6.

Can you tell us how to obtain maximum performance for reads from a PCIe EP using the i.MX6 RC?

Thanks

Re: PCIe READ PROBLEM FROM IMX6.SOLOX

igorpadykov — Tue, 12 Sep 2017 04:10:32 GMT

Hi Steve

for improving performance one can try to use dma, described on

https://community.nxp.com/docs/DOC-95014

Best regards
igor
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Re: PCIe READ PROBLEM FROM IMX6.SOLOX

steveretzlaff — Tue, 12 Sep 2017 21:36:35 GMT

Thanks for the response.

However, from what we gather, the I.MX6 SoloX chip does not have an IPU, so it cannot be used for DMA.

In addition according to what we have read elsewhere on the NXP Community forum, the I.MX6 SDMA engine cannot be used to perform DMA to or from the PCIe module.

Re: PCIe READ PROBLEM FROM IMX6.SOLOX

igorpadykov — Tue, 12 Sep 2017 23:40:54 GMT

you are right I missed that it was SoloX, sorry. In general for performance issues

one can try to apply to NXP Professional Services:

http://www.nxp.com/support/nxp-professional-services:PROFESSIONAL-SERVICE

Best regards
igor