<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: How to link code to DDR (start address 0x80000000) on Cortex M4 side in IMX7D</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698177#M108415</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Chandini,&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;Please refer to my similar question here:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/message/921361"&gt;https://community.nxp.com/message/921361&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 24 Aug 2017 21:29:18 GMT</pubDate>
    <dc:creator>ryanschaefer</dc:creator>
    <dc:date>2017-08-24T21:29:18Z</dc:date>
    <item>
      <title>How to link code to DDR (start address 0x80000000) on Cortex M4 side in IMX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698175#M108413</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have modified &amp;nbsp;"&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;MCIMX7D_M4_ddr.ld " as follow&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;MEMORY&lt;BR /&gt;{&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x0001FFFF&amp;nbsp;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;m_data (RW) : ORIGIN = 0x20210000, LENGTH = 0x00010000&amp;nbsp;&lt;BR /&gt;}&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;there is no error when I compile the code, but the process can not start up when I load the binary file to 0x80000000 on uboot. I load file as follow:&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;tftp 0x80000000 example.bin;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;dcache flush; &lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;bootaux 0x80000000&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;M4 core starts up and i can see my starting printf &amp;nbsp;in M4 terminal&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;i did change imx7d-sdb.dts and imx7d-sdb-m4.dts&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;Changed from&amp;nbsp;&lt;EM style="color: #3d3d3d;"&gt;0x80000000&lt;SPAN&gt;&amp;nbsp; to&amp;nbsp;0x80100000&amp;nbsp; in both files&lt;/SPAN&gt;&lt;/EM&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;in imx7d-sdb.dts&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;memory {&lt;BR /&gt; reg = &amp;lt;0x80100000 0x80000000&amp;gt;;&lt;BR /&gt; };&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;in&amp;nbsp;imx7d-sdb-m4.dts:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="background-color: #ffffff; color: #333333; font-size: 14px;"&gt;memory {&lt;BR /&gt; linux,usable-memory = &amp;lt;0x80100000 0x1ff00000&amp;gt;,&amp;nbsp;&lt;BR /&gt; &amp;lt;0xa0000000 0x1ff00000&amp;gt;;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;But linux hangs here&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;** Unable to read file boot.scr **&lt;BR /&gt;reading zImage&lt;BR /&gt;6619128 bytes read in 326 ms (19.4 MiB/s)&lt;BR /&gt;Booting from mmc ...&lt;BR /&gt;reading imx7d-sdb-m4.dtb&lt;BR /&gt;46439 bytes read in 35 ms (1.3 MiB/s)&lt;BR /&gt;Kernel image @ 0x80800000 [ 0x000000 - 0x64fff8 ]&lt;BR /&gt;## Flattened Device Tree blob at 83000000&lt;BR /&gt; Booting using the fdt blob at 0x83000000&lt;BR /&gt; Using Device Tree in place at 83000000, end 8300e566&lt;/P&gt;&lt;P&gt;Starting kernel ...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could anyone please what changes i have to do to USE starting of DDR for only M4 ? any disable linux access to that memory ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you in advance&lt;/P&gt;&lt;P&gt;Chandini&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 14 Aug 2017 09:17:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698175#M108413</guid>
      <dc:creator>chandiniindavar</dc:creator>
      <dc:date>2017-08-14T09:17:01Z</dc:date>
    </item>
    <item>
      <title>Re: How to link code to DDR (start address 0x80000000) on Cortex M4 side in IMX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698176#M108414</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Chandini,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;IMX6SX provides also Cortex-M4 as IMX7D does. The following document will be useful:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.nxp.com/docs/en/application-note/AN5127.pdf" title="http://www.nxp.com/docs/en/application-note/AN5127.pdf"&gt;http://www.nxp.com/docs/en/application-note/AN5127.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For further details please provide information details about how are you developing M4 application. What compiler are you using, which IDE, is it based on an example application?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Carlos&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Aug 2017 20:54:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698176#M108414</guid>
      <dc:creator>Carlos_Musich</dc:creator>
      <dc:date>2017-08-23T20:54:09Z</dc:date>
    </item>
    <item>
      <title>Re: How to link code to DDR (start address 0x80000000) on Cortex M4 side in IMX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698177#M108415</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Chandini,&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;Please refer to my similar question here:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/message/921361"&gt;https://community.nxp.com/message/921361&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Aug 2017 21:29:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698177#M108415</guid>
      <dc:creator>ryanschaefer</dc:creator>
      <dc:date>2017-08-24T21:29:18Z</dc:date>
    </item>
    <item>
      <title>Re: How to link code to DDR (start address 0x80000000) on Cortex M4 side in IMX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698178#M108416</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Ryan and Carlos .&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Sep 2017 14:59:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-link-code-to-DDR-start-address-0x80000000-on-Cortex-M4/m-p/698178#M108416</guid>
      <dc:creator>chandiniindavar</dc:creator>
      <dc:date>2017-09-04T14:59:57Z</dc:date>
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  </channel>
</rss>

