Interrupt priorities in INTC (Interrupt Controller)

adityanagal — Fri, 08 Sep 2017 11:19:33 GMT

Hi ,

I am going through the IMX6 solo reference manual. In section 28.7 , I could see details of IRQ masking register , Status Register and control register . I could not see any details about Interrupt Priorities. My queries are below mentioned :

Q1. What if multiple interrupts come simultaneously on IRQ lines , how INTC will generate the wakeup signal then.

Q2. If CPU is serving interrupt from one resource , it is executing its ISR and at that time , if any other interrupt comes from another IRQ line , will it prempt the current execution of ISR and jump to serve another ?

Please suggest.

Regards,

Aditya Nagal

Re: Interrupt priorities in INTC (Interrupt Controller)

igorpadykov — Fri, 08 Sep 2017 23:17:53 GMT

Hi Aditya

>Q1. What if multiple interrupts come simultaneously on IRQ lines , how INTC will generate the wakeup signal then.

both interrupts will wake processor.

Q2.>

INTC interrupts are used only for wake, when processor is not executing any ISR code,

staying in wait for interrupt (WFI) instruction. According to sect.28.6 GPC Interrupt Controller

(INTC) i.MX6SDL Reference Manual :
The INTC (Interrupt Controller) detects an interrupt and generates the wakeup signal. It
supports up to 128 interrupts.

http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf

Best regards
igor
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topic Re: Interrupt priorities in INTC (Interrupt Controller) in i.MX Processors

Interrupt priorities in INTC (Interrupt Controller)

Re: Interrupt priorities in INTC (Interrupt Controller)