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    <title>topic Re: IMX6ULL ECSPI Timings in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697678#M108320</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We ran into the same issue, not expecting the assymetry in the use of read/write.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;60Mhz can only be achieved if MISO is not used.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 18 Dec 2017 10:31:26 GMT</pubDate>
    <dc:creator>arnoutdiels</dc:creator>
    <dc:date>2017-12-18T10:31:26Z</dc:date>
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      <title>IMX6ULL ECSPI Timings</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697676#M108318</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm trying to understand what the maximum rate is that the IMX6ULL can receive data over the SPI port,&amp;nbsp;and need some clarification on how to interpret the timing parameters.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In section 4.12.2 of the&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/data-sheet/IMX6ULLIEC.pdf"&gt;6ULL Datasheet&lt;/A&gt;, Table 47 "ECSPI Master Mode Timing Parameters" has&amp;nbsp;an SCLK cycle period of 43ns for a read, and 15ns for a write.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;Table 48 "&lt;/SPAN&gt;&lt;SPAN&gt;ECSPI&amp;nbsp;Slave Mode Timing Parameters" has&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;an SCLK cycle period of 15ns for a read, and 43ns for a write.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;15ns allows a ~66MHz max SCLK. 43ns allows a ~23MHz max SCLK. My application requires 26Mbps read into the 6ULL, so I need to confirm what the 6ULL is capable of.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The relative direction of "read" and "write" is what's causing the confusion. In Table 48 (slave mode), do I interpret&amp;nbsp;"read" as relative to the 6ULL, meaning 66MHz max clock when reading data into the device? Or is it relative to the&amp;nbsp;master device, therefore SCLK&amp;nbsp;is 23MHz when reading into the 6UL?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, how do these timings relate to the "52Mbps" specified in Table2?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Oct 2017 19:17:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697676#M108318</guid>
      <dc:creator>jonhallam</dc:creator>
      <dc:date>2017-10-03T19:17:40Z</dc:date>
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    <item>
      <title>Re: IMX6ULL ECSPI Timings</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697677#M108319</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; The i.MX6ULL Datasheet provides correct specs regarding eCSPI maximal frequency,&lt;/P&gt;&lt;P&gt;which is different for read and write ops. Read and write are considered relatively i.MX6ULL -&lt;/P&gt;&lt;P&gt;Your interpretation is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Also You may look at &lt;A href="https://community.nxp.com/docs/DOC-95461"&gt;https://community.nxp.com/docs/DOC-95461&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Oct 2017 06:44:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697677#M108319</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-10-05T06:44:42Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL ECSPI Timings</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697678#M108320</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We ran into the same issue, not expecting the assymetry in the use of read/write.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;60Mhz can only be achieved if MISO is not used.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Dec 2017 10:31:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697678#M108320</guid>
      <dc:creator>arnoutdiels</dc:creator>
      <dc:date>2017-12-18T10:31:26Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL ECSPI Timings</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697679#M108321</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I likewise have the same question in relation to the i.MX6UL.&lt;/P&gt;&lt;P&gt;I suspect table 48 may has a typo.&amp;nbsp; I looked at the i.MX6DL datasheet&amp;nbsp;and both Master and Slave have identical SCLK cycle period of 43ns for a read, and 15ns for a write.&amp;nbsp; If this is true then Read can never exceed 23 Mbps.&lt;/P&gt;&lt;P&gt;Jon Hallam - Did you ever get this tested?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 Jan 2018 20:25:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-ECSPI-Timings/m-p/697679#M108321</guid>
      <dc:creator>johnbaczewski</dc:creator>
      <dc:date>2018-01-24T20:25:14Z</dc:date>
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