topic Re: IMX7D power saving mode result in i.MX Processors

IMX7D power saving mode result

frankyhsu — Mon, 19 Jun 2017 10:53:35 GMT

Hi Support,

1. DSM mode

We are trying to get some testing data on DSM mode description in AN5383. We set "echo mem > /sys/power/state" and measure the result. Each power rail to IMX7D pins look well except the VDD_SOC that is still about 60mA. Seems the VDD_SOC is not in the right idle mode. How do we check it?

2. normal mode

After power on, the system will run system idle mode when no thread, we can see the VDD_ARM is about 5mA, it's acceptable for us, but we found the VDD_SOC is about 200mA. It's so large and just like we run 100% on M4 processor but we do nothing. How do we check it?

Thanks.

Re: IMX7D power saving mode result

igorpadykov — Mon, 19 Jun 2017 23:25:19 GMT

Hi Franky

VDD_SOC is power domain for almost all peripherals, please refer

Figure 5-10. i.MX7Dual Power Domains, Table 5-5. Low Power Mode Definition
i.MX7D Reference Manual
http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf
one can check that for VDD_SOC current is measured on R24, VDD_SOC is reduced to 0.925 V.

It is possible try to disable modules one by one and check if it reduces current.

2. please check that M4 is running some code, as it is also powered by VDD_SOC

Best regards
igor
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Re: IMX7D power saving mode result

frankyhsu — Mon, 26 Jun 2017 02:19:30 GMT

We also use VDD_SOC to supply the PCIE_VP which is used for BDSL support, is it possible to be a issue for losing power when set to low power mode?

The NVCC_1V8 also supplies to PCIE_VPH for BDSL support and the NVCC_1V8 can keep to save power without additional loss.

Re: IMX7D power saving mode result

frankyhsu — Fri, 30 Jun 2017 08:39:54 GMT

Any update for my question for this connection?

2. For VDD_SOC drop to 0.925V, do we need to configure it? Or if we can enter the DSM, the VDD_SOC will drop to 0.925 automatically? Sure, we need to make sure that all function is disabled.

3. In AN5383, table 2 shows the VDD_soc is 0.975 but should it be 0.925V or the 0.975V is just a typo?

Re: IMX7D power saving mode result

igorpadykov — Fri, 30 Jun 2017 10:53:04 GMT

-there is no need to change VDD_SOC as linux automatically sets it,

please check sect.6.1. Deep-Sleep mode AN5383

- why do you think that it should be 0.925V ? Please check

Table 9. Operating ranges i.MX7D Datasheet

http://cache.nxp.com/files/32bit/doc/data_sheet/IMX7DCEC.pdf

~igor

Re: IMX7D power saving mode result

frankyhsu — Fri, 30 Jun 2017 11:16:08 GMT

1. That's our question, since we use echo mem > /sys/power/state to set DSM mode, why do we still need to check if we disable all the function. Does this mode not disable all function automatically and we need to disable all function first to let the "echo mem > /sys/power/state" command work?

2. - why do you think that it should be 0.925V ? Please check.

>> The table 2 in AN5383 shows the DSM result but the table shows the VDD_soc is 0.974V. Is it a typo since the DSM should be 0.925V?

Re: IMX7D power saving mode result

igorpadykov — Fri, 30 Jun 2017 12:21:26 GMT

- one can look at Chapter 21 Low-level Power Management (PM) Driver

attached Linux Manual for sources low power driver.

- VDD_SOC should be 0.95V according to Table 9. Operating ranges

i.MX7D Datasheet

http://cache.nxp.com/files/32bit/doc/data_sheet/IMX7DCEC.pdf

>We also use VDD_SOC to supply the PCIE_VP which is used for BDSL support, is it possible

>to be a issue for losing power when set to low power mode?

I believe yes. To be sure suggest to disconnect and connect as it is done on i.MX7D SabreSD schematic.

Re: IMX7D power saving mode result

frankyhsu — Mon, 03 Jul 2017 02:57:28 GMT

In An5383, it shows the VDD_SOC will reduce to 0.925V, is it wrong?

>We also use VDD_SOC to supply the PCIE_VP which is used for BDSL support, is it possible

>to be a issue for losing power when set to low power mode?

I believe yes. To be sure suggest to disconnect and connect as it is done on i.MX7D SabreSD schematic.

--It's a bad news for us that we do not have 0 ohm to the PCIE_VP. The NVCC_1v8 also connects to PCIE_VPH for the same purpose with PCIE_VP but the NVCC_1V8 can have ultra low power consumption when set to DSM. It the VDD_SOC will still have high current on DSM mode due to PCIE_VP, the NVCC_1V8 should have similar result but it does not. Do you have any idea to disable the related function used for PCIE_VP to check if we can let the PCIE_VP to stop to sink the current for VDD_soc?

Re: IMX7D power saving mode result

igorpadykov — Mon, 03 Jul 2017 04:37:32 GMT

yes, it is misprint. Correct value is given in Datasheet.

Regarding PCIE_VP connections probably you can imitate behaviour on SabreSD board.

~igor

Re: IMX7D power saving mode result

frankyhsu — Mon, 03 Jul 2017 05:43:53 GMT

1.So, the VDD_SOC power = 0.975V will not be changed whatever the M4 stay idle or active or high loading mode?

2. In Saber board, the net connect to VDDD_1p0_cap, it seems that we can not supply the VDD_soc to the PCIE_VP directly.

Re: IMX7D power saving mode result

igorpadykov — Mon, 03 Jul 2017 05:59:58 GMT

- according to sect.4.1.1. Use case 1: Deep-Sleep Mode (DSM) AN5383 :

- the M4 is idle.

- you can measure VDDD_1p0_cap on SabreSD board in DSM mode

~igor

Re: IMX7D power saving mode result

frankyhsu — Thu, 13 Jul 2017 02:56:22 GMT

We use Saber board to do the experiment, we check the internal LDO VDDD_1P0_CAP power rail will be disabled and we supply external 1.0V to supply the below power rail and found the there are extra current flow to this power power rail about 20mA. The VDD_SOC on our board has 65mA, if we remove this additional 20mA, there is 44mA which is still loss in the system in suspend mode. Do you have any idea for it?

Re: IMX7D power saving mode result

igorpadykov — Thu, 13 Jul 2017 05:16:54 GMT

Hi Franky

since VDDD_1P0_CAP power is applied in your case, it may

influence on other processor power rails (domains), causing bigger currents

form them, due to parasitic voltages leaking from powered VDDD_1P0_CAP block

to other processor power domains.

Unfortunately there are no estimations for such additional power consumption.

Best regards
igor

Re: IMX7D power saving mode result

frankyhsu — Thu, 27 Jul 2017 07:00:48 GMT

Hi Igor, we are also checking the additional power consumption on I/Os, I mean NVCC_1V8 and NVCC_3V3 to supply the NVCC_xxxx for I/O power as below:

Since we do not leave 0 ohm here but we can still measure some current on NVCC_1V8. Except these NVCC_xxx, we has disconnected the power connection for all peripheral devices. So, it seems there is still some power going into the power pins as show below when we go into DSM mode.

My question is, do we need to turn off the data bus before we excuse the DSM command? Or the DSM will auto turn off the I/O operation to save the power?

Does this power rail for NVCC_xxx have chance to consume power more than 10mA?

Re: IMX7D power saving mode result

igorpadykov — Thu, 27 Jul 2017 10:34:14 GMT

Hi Franky

please check Table 5-4. Power Mode i.MX7D Reference Manual

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

Best regards
igor

Re: IMX7D power saving mode result

frankyhsu — Fri, 28 Jul 2017 11:11:10 GMT

To turn off the integrated PMU before enter the DSM mode since they are all on in default?

Re: IMX7D power saving mode result

igorpadykov — Fri, 28 Jul 2017 11:36:19 GMT

most voltages are ON, but almost all modules are disabled. Its clocks are turned off.

You can measure voltages on nxp i.MX7D Sabre reference board.

Re: IMX7D power saving mode result

frankyhsu — Fri, 28 Jul 2017 11:39:46 GMT

I mean, does "to turn off PVCC_xxx" help to save the power? Do I have chance to turn off them by SW?

Re: IMX7D power saving mode result

igorpadykov — Fri, 28 Jul 2017 12:11:25 GMT

according to sect.4.1.6 Power modes i.MX7D Datasheet :

The NVCC_XXX can be off in RUN mode / Low Power mode if all the pads in that IO bank is not used
in the application, the NVCC_XXX supply could be tied to GND.

Re: IMX7D power saving mode result

frankyhsu — Mon, 31 Jul 2017 02:16:44 GMT

I mean can we turn off NVCC_XXX internally even the PVCC by SW setting? The description mentioned that to turn off the NVCC_XXX by externally circuit?

If we want the imx7D to get ultra low power result for all power rail supplied to the chip, do we need to add external power circuit to close the unused I/O pad? Which power pad does need the external switch and which one does not need it? The AN5383 does not provide the I/O pad measurement result, I know it is because the Saber function is different from customer's design.

I think it's not clear in the application note. Do we need to add external power switch to turn off the I/O power pad?