Reg: Touch Screen

arjunk — Tue, 11 Jul 2017 08:49:39 GMT

Hi All,

I am interested in interfacing Touch Screen with my EVB. I am getting Display in my screen, but not able to use Touch Screen.

I am using I.MX 6Q SABRE SDB,Kernel -4.1.15,and for rootfs buildroot

TSC2004 TOUCH SCREEN CONTROLLER

Kindly advice how to enable and calibrate for touch screen.

Arjun k_

Re: Reg: Touch Screen

ramyaravichandr — Thu, 14 Sep 2017 12:49:58 GMT

Hi Arjun,

It would be great if you could throw more light on the following:

1. Have you added the touch panel details in the device tree?

2. Was the interrupt for the touch panel configured?

Thanks,

Ramya

Re: Reg: Touch Screen

Rita_Wang — Thu, 14 Sep 2017 12:59:23 GMT

You can refer to i.MX_Linux_Release_Notes.

Re: Reg: Touch Screen

arjunk — Mon, 09 Oct 2017 11:22:02 GMT

i added in dtsi file but am not geting the interrupt when am toching .

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;

iomuxc_imx6q_sabrelite: iomuxc-imx6q-sabrelitegrp {
status = "okay";
};
};

&iomuxc_imx6q_sabrelite {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
>;
};

pinctrl_audmux_tc358743: audmux-tc358743grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0
MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
>;
};

pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1
#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1
>;
};

pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
#define GP_ENET_PHY_RESET <&gpio3 23 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x030b0
#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW>
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
>;
};

pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
#define GP_FLEXCAN1_STANDBY <&gpio1 2 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0b0b0 /* CAN enable */
>;
};

pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
#define GP_GPIOKEY_POWER <&gpio2 3 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
#define GP_GPIOKEY_MENU <&gpio2 1 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
#define GP_GPIOKEY_HOME <&gpio2 4 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
#define GP_GPIOKEY_BACK <&gpio2 2 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
#define GP_GPIOKEY_VOL_UP <&gpio7 13 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
#define GP_GPIOKEY_VOL_DN <&gpio4 5 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};

pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 /* Spare */
>;
};

pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};

pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */
>;
};

pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};

pinctrl_i2c2_ov5640_mipi: i2c2-ov5640-mipigrp {
fsl,pins = <
#define GP_OV5640_MIPI_POWER_DOWN <&gpio6 9 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
#define GP_OV5640_MIPI_RESET <&gpio2 5 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
>;
};

pinctrl_i2c2_ov5642: i2c2-ov5642grp { /* parallel camera */
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* mclk */
#define GP_OV5642_POWER_DOWN <&gpio1 6 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0
#define GP_OV5642_RESET <&gpio1 8 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0
>;
};

pinctrl_i2c2_tc358743_mipi: i2c2-tc358743_mipigrp {
fsl,pins = <
#define GP_TC3587_RESET <&gpio6 9 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x030b0
#define GPIRQ_TC3587 <&gpio2 5 IRQ_TYPE_LEVEL_LOW>
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b0
>;
};

pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */
>;
};

pinctrl_i2c3_adv7180_gpios: i2c3-adv7180_gpiosgrp {
fsl,pins = <
/* No data enable pin, make sure it is not selected */
MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x0b0b1
#define GP_ADV7180_PWN <&gpio3 13 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0
#define GP_ADV7180_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0
#define GPIRQ_ADV7180 <&gpio5 0 IRQ_TYPE_LEVEL_LOW>
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
>;
};

pinctrl_i2c3_adv7180: i2c3-adv7180grp {
/* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */
};

pinctrl_i2c3_adv7180_cea861: i2c3-adv7180_cea861grp {
/* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */
};

pinctrl_i2c3_adv7180_no_cea861: i2c3-adv7180_no_cea861grp {
fsl,pins = <
MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0xb0b1 /* Hsync */
MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0xb0b1 /* Vsync */
>;
};

pinctrl_i2c3_ov5640: i2c3-ov5640grp {
/* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */
};

pinctrl_i2c3_ov5640_gpios: i2c3-ov5640-gpiosgrp {
fsl,pins = <
#define GP_OV5640_POWER_DOWN <&gpio3 13 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0
#define GP_OV5640_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0
>;
};

pinctrl_i2c3_tsc2004: i2c3-tsc2004grp {
fsl,pins = <
#define GPIRQ_TSC2004 <&gpio4 20 IRQ_TYPE_EDGE_FALLING>
#define GP_TSC2004 <&gpio4 20 GPIO_ACTIVE_LOW>
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */
>;
};

pinctrl_lcd0: lcd0grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};

pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PW

Re: Reg: Touch Screen

arjunk — Fri, 29 Dec 2017 06:24:04 GMT

Hi ,

am added the touch screen controller ( TSC2004 ) in device tree , using build root for building linux , even x server also enabled .

The interrupt configuration it ill take automatically or i have to do manually ?.
right now the interrupt is configured automatically.

am getting the interrupt one of the side in touch screen .

Kindly advice how to enable and calibrate for touch screen.

Arjun k

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