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    <title>i.MX ProcessorsのトピックCPMEM control registers</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/CPMEM-control-registers/m-p/690719#M106989</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i found a similar post in this forum, yet no answer was provided.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In&amp;nbsp;IMX6DQRM.pdf I am trying to find where the CPMEM registers (there should be a total of 2*5*80 registers of 32bit per IPU).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With debug enabled, dmesg prints the following:&lt;/P&gt;&lt;P&gt;Jun &amp;nbsp;8 13:54:10 &amp;nbsp;kernel: imx-ipuv3 2400000.ipu: initializing idma ch 21 @ c0900540.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0x0240_0000 is the base address of IPU1, despite&amp;nbsp;37.5 IPU Memory Map/Register Definition placing at at &lt;A href="mailto:0x0@^"&gt;0x&lt;/A&gt;0260_0000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0xC090_0540 seems to be the offset for -probably- the first REGISTER for the CPMEM for IDMA channel 21 in IPU1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would hence expect channel 0 on 0xC090_0000. This may be the virtual address of course, otherwise I can not relate this to IPU1 at all.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, i do not find CPMEM at all in&amp;nbsp;37.5 IPU Memory Map/Register Definition. Could you point to it? In other posts the reply is "use this address it works", but i would like to find it in documentation".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;KR&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Jean Mitchel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 17 Jun 2017 11:29:30 GMT</pubDate>
    <dc:creator>jeanmitchel</dc:creator>
    <dc:date>2017-06-17T11:29:30Z</dc:date>
    <item>
      <title>CPMEM control registers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CPMEM-control-registers/m-p/690719#M106989</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i found a similar post in this forum, yet no answer was provided.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In&amp;nbsp;IMX6DQRM.pdf I am trying to find where the CPMEM registers (there should be a total of 2*5*80 registers of 32bit per IPU).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With debug enabled, dmesg prints the following:&lt;/P&gt;&lt;P&gt;Jun &amp;nbsp;8 13:54:10 &amp;nbsp;kernel: imx-ipuv3 2400000.ipu: initializing idma ch 21 @ c0900540.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0x0240_0000 is the base address of IPU1, despite&amp;nbsp;37.5 IPU Memory Map/Register Definition placing at at &lt;A href="mailto:0x0@^"&gt;0x&lt;/A&gt;0260_0000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0xC090_0540 seems to be the offset for -probably- the first REGISTER for the CPMEM for IDMA channel 21 in IPU1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would hence expect channel 0 on 0xC090_0000. This may be the virtual address of course, otherwise I can not relate this to IPU1 at all.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, i do not find CPMEM at all in&amp;nbsp;37.5 IPU Memory Map/Register Definition. Could you point to it? In other posts the reply is "use this address it works", but i would like to find it in documentation".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;KR&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Jean Mitchel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 17 Jun 2017 11:29:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CPMEM-control-registers/m-p/690719#M106989</guid>
      <dc:creator>jeanmitchel</dc:creator>
      <dc:date>2017-06-17T11:29:30Z</dc:date>
    </item>
    <item>
      <title>Re: CPMEM control registers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CPMEM-control-registers/m-p/690720#M106990</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp; please refer to &lt;SPAN class=""&gt;Qiang Li answer in the following thread&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/357621"&gt;Writing to the IPU's CPMEM region&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Jun 2017 04:24:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CPMEM-control-registers/m-p/690720#M106990</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-19T04:24:06Z</dc:date>
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