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    <title>i.MX ProcessorsのトピックRe: DDR stress test error</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DDR-stress-test-error/m-p/688658#M106604</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Since "pattern should match address " - high two bytes do not match in Your case.&lt;/P&gt;&lt;P&gt;Look at U2 (16~31 bit) and U4&amp;nbsp; (48~63 bit).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Also, please try to check the design, using section 1.1 (Schematic and Layout Design Rules) of the DDR3 &lt;BR /&gt;Porting Guide&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; In particular, there is an Excel page named “MX6 DRAM Bus Length Check” in “HW Design Checking List &lt;BR /&gt;for i.Mx6”. Designer can use it for layout self-checking. Input trace length of the design into cells in pink circle then, the bottom cell in same column may change to red color if layout breaks the rule.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Recent design checklist may be found at&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93819"&gt;HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 16 Jun 2017 08:04:57 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-06-16T08:04:57Z</dc:date>
    <item>
      <title>DDR stress test error</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR-stress-test-error/m-p/688657#M106603</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;DDR3 layout same as SabreSD board.&lt;BR /&gt;Four (U1~U4) 16-bits DDR3 with one chip select.&lt;BR /&gt;U1 is 0~15 bit&lt;BR /&gt;U2 is 16~31 bit&lt;BR /&gt;U3 is 32~47 bit&lt;BR /&gt;U4 is 48~63 bit&lt;BR /&gt;&lt;BR /&gt;DDR Freq: 396 MHz&lt;BR /&gt;t0.1: data is addr test&lt;BR /&gt;Address of failure: 0x4f9e5f84&lt;BR /&gt;Data was: 0x00005f84&lt;BR /&gt;But pattern should match address &lt;BR /&gt;Error: failed to run stress test!!!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;May we know which DDR3 chip has issue?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Jun 2017 07:45:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR-stress-test-error/m-p/688657#M106603</guid>
      <dc:creator>m_c</dc:creator>
      <dc:date>2017-06-16T07:45:06Z</dc:date>
    </item>
    <item>
      <title>Re: DDR stress test error</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR-stress-test-error/m-p/688658#M106604</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Since "pattern should match address " - high two bytes do not match in Your case.&lt;/P&gt;&lt;P&gt;Look at U2 (16~31 bit) and U4&amp;nbsp; (48~63 bit).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Also, please try to check the design, using section 1.1 (Schematic and Layout Design Rules) of the DDR3 &lt;BR /&gt;Porting Guide&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; In particular, there is an Excel page named “MX6 DRAM Bus Length Check” in “HW Design Checking List &lt;BR /&gt;for i.Mx6”. Designer can use it for layout self-checking. Input trace length of the design into cells in pink circle then, the bottom cell in same column may change to red color if layout breaks the rule.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Recent design checklist may be found at&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93819"&gt;HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Jun 2017 08:04:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR-stress-test-error/m-p/688658#M106604</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-16T08:04:57Z</dc:date>
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