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    <title>topic Re: MX7D SABRE RGMII2 modification in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687794#M106535</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lars&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in general you are right:&lt;/P&gt;&lt;P&gt;ENET2 signals are multiplexed with EPDC signals and are accessible&amp;nbsp;through the EPDC connector,&lt;/P&gt;&lt;P&gt;U36 enables RGMII2 signals using ENET_EN_B (GPIO1_IO04).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 07 Jul 2017 23:52:03 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-07-07T23:52:03Z</dc:date>
    <item>
      <title>MX7D SABRE RGMII2 modification</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687793#M106534</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Community!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BACKGROUND:&lt;/P&gt;&lt;P&gt;Before creating custom MX7D hardware from scratch I would like to create an addon board for the SABRE and test custom peripherals. This way,&amp;nbsp;all peripherals can be tested with a known-to-work base platform. Once the peripherals are tested, the SoC/RAM/memory etc circuitry/hardware will be created and combined with the peripherals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ETHERNET:&lt;/P&gt;&lt;P&gt;One of the peripherals is Ethernet and i would like to test my Ethernet Phy circuitry on the addon board.&lt;/P&gt;&lt;P&gt;SMI and RMII signals are needed.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;SMI:&lt;UL&gt;&lt;LI&gt;To access the SMI interface a wire could be connected to R271 (pullup MDIO) and R495 (Termination MDC).&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;RMII:&lt;UL&gt;&lt;LI&gt;ENET2 signals are multiplexed with EPDC signals and should be accessible&amp;nbsp;through the EPDC connector.&lt;/LI&gt;&lt;LI&gt;I need to cut the connection of ENET2 and the SABRE Ethernet Phy. how may i do this? remove U36?&lt;/LI&gt;&lt;LI&gt;Are any additional steps necessary to access the signals? (e.g. adding resistors/bridges)&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 10:02:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687793#M106534</guid>
      <dc:creator>demoniacmilk</dc:creator>
      <dc:date>2017-07-07T10:02:47Z</dc:date>
    </item>
    <item>
      <title>Re: MX7D SABRE RGMII2 modification</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687794#M106535</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lars&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in general you are right:&lt;/P&gt;&lt;P&gt;ENET2 signals are multiplexed with EPDC signals and are accessible&amp;nbsp;through the EPDC connector,&lt;/P&gt;&lt;P&gt;U36 enables RGMII2 signals using ENET_EN_B (GPIO1_IO04).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 23:52:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687794#M106535</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-07-07T23:52:03Z</dc:date>
    </item>
    <item>
      <title>Re: MX7D SABRE RGMII2 modification</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687795#M106536</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;So if i pull GPIO1_IO04 high, then U36 "cuts" the connection between Phy and MX7?&lt;BR /&gt;Sounds good. Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Jul 2017 11:14:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MX7D-SABRE-RGMII2-modification/m-p/687795#M106536</guid>
      <dc:creator>demoniacmilk</dc:creator>
      <dc:date>2017-07-11T11:14:18Z</dc:date>
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