topic Re: iMX6 SPI Read Timing Issue in i.MX Processors

iMX6 SPI Read Timing Issue

narasimma2 — Fri, 28 Jul 2017 13:27:39 GMT

Hi I'm using iMX6 Quad with Linux Kernel 3.14.38, i'm trying to read data from ADC chip through SPI interface, i'm having the throughput issue, so when i probed on the scope each SPI read takes more than 70 microseconds, but our requirement is read 128bit data less than 20 microseconds.

Find the attached Timing snapshot between SCLK and Chip Select.

It consumes more time on following operations,

SPI Read call to CS Low
CS Low to First SCLK
Last SCLK to CS High
CS High to SPI Read call finished

Please help me to resolve this issue.

Re: iMX6 SPI Read Timing Issue

igorpadykov — Sat, 29 Jul 2017 00:41:06 GMT

Hi Narasimma

for increasing performance one can try to use bursts,

please look at BURST_LENGTH description in

sect.20.7.3 Control Register (ECSPIx_CONREG) i.MX6UL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: iMX6 SPI Read Timing Issue

narasimma2 — Mon, 31 Jul 2017 11:57:29 GMT

Hi igor,

Thanks for reply,

We tried changing BURST_LENGTH to 128 bits. But IMX SPI driver is restricting it to 32 bits & it doesn't solve our issue. Our primary issue is that even for 8-bit BURST_LENGTH, we are not getting typical SPI Burst as per Figure 20-4 (page-776) in Ref Manual : http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf. Please refer our attached snapshot and help us in resolving why we are facing delay in uSecs between SCLK & CS signals.