<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Additional Chip Select lines for SPI interface in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Additional-Chip-Select-lines-for-SPI-interface/m-p/686852#M106307</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are developing one of our product using CM-FX6 &amp;nbsp;( IMX6 Quad based COM form Compulab), is it possible to use available GPIO lines for additional Chip select lines for SPI interface required, the dedicated Chip select lines of SPI are used for some other interfaces in our design.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Harish.S&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 22 May 2017 07:24:24 GMT</pubDate>
    <dc:creator>harishs</dc:creator>
    <dc:date>2017-05-22T07:24:24Z</dc:date>
    <item>
      <title>Additional Chip Select lines for SPI interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Additional-Chip-Select-lines-for-SPI-interface/m-p/686852#M106307</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are developing one of our product using CM-FX6 &amp;nbsp;( IMX6 Quad based COM form Compulab), is it possible to use available GPIO lines for additional Chip select lines for SPI interface required, the dedicated Chip select lines of SPI are used for some other interfaces in our design.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Harish.S&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 May 2017 07:24:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Additional-Chip-Select-lines-for-SPI-interface/m-p/686852#M106307</guid>
      <dc:creator>harishs</dc:creator>
      <dc:date>2017-05-22T07:24:24Z</dc:date>
    </item>
    <item>
      <title>Re: Additional Chip Select lines for SPI interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Additional-Chip-Select-lines-for-SPI-interface/m-p/686853#M106308</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; It is possible to use available GPIO lines for additional Chip select lines for SPI interface. &lt;BR /&gt;But users should control these GPIO lins in software.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 May 2017 08:00:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Additional-Chip-Select-lines-for-SPI-interface/m-p/686853#M106308</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-05-22T08:00:04Z</dc:date>
    </item>
  </channel>
</rss>

