DDR3 T Branch routing

jozef_s — Mon, 12 Jun 2017 14:59:05 GMT

Hello,

I have a question about routing topology of DDR3. In design I use two DDR3s, which are connected in T branch topology. Then termination and extra Vtt regulator are not necessary.

Should the address trace (ADDR0..ADDR15) from T branch to both memories the same length?

Thanks!

jozef

Re: DDR3 T Branch routing

gusarambula — Mon, 12 Jun 2017 16:56:20 GMT

Hello Jozef Szigl,

Yes, when using T topology, the address signals should be the same length for all DDR chips. There is some margin, You don’t mention which processor you are using but for the i.MX6 for example address traces routing should match with a ± 25 mils margin.

You can find more details on recommended routing for the i.MX6 on the HW Design Guide (link below), although these are not unique to the i.MX6.

http://www.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf

I hope this helps!

Regards,

topic DDR3 T Branch routing in i.MX Processors

DDR3 T Branch routing

Re: DDR3 T Branch routing