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    <title>topic Re: IMX6S + LPDDR2 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682198#M105404</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi zhang&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please run ddr test and update *.cfg file with new calibration settings found from test&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-105652"&gt;https://community.nxp.com/docs/DOC-105652&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Jul 2017 23:40:14 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-07-25T23:40:14Z</dc:date>
    <item>
      <title>IMX6S + LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682197#M105403</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff; font-size: small;"&gt;Dear,everyone,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff; font-size: small;"&gt;&amp;nbsp; &amp;nbsp; I designed a board with imx6s + lpddr2。The uboot can booting now，but the kernel is hanging at "Uncompressing Linux... done, booting the kernel".T&lt;/SPAN&gt;&lt;SPAN style="color: #000000; background-color: #ffffff; font-size: small;"&gt;he uboot output log , DCD config table and Schematic ,pls refer to the attachment.&amp;nbsp;and give me some advise!.&lt;/SPAN&gt;&lt;SPAN style="background-color: #ffffff; color: #000000; font-size: small;"&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Original Attachment has been moved to: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-336406"&gt;uboot-log.txt.zip&lt;/A&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Original Attachment has been moved to: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-336406"&gt;imximage_mx6dl.cfg.zip&lt;/A&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Jul 2017 12:18:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682197#M105403</guid>
      <dc:creator>zhanghaijian</dc:creator>
      <dc:date>2017-07-25T12:18:17Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6S + LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682198#M105404</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi zhang&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please run ddr test and update *.cfg file with new calibration settings found from test&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-105652"&gt;https://community.nxp.com/docs/DOC-105652&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Jul 2017 23:40:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682198#M105404</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-07-25T23:40:14Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6S + LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682199#M105405</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello igor,&lt;/P&gt;&lt;DIV style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;I tested the memory with the &amp;#147;i.MX6/7 DDR Stress Test Tool V2.70&amp;#148;，The output log is：&lt;/DIV&gt;&lt;DIV style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt; &lt;/DIV&gt;&lt;DIV style="color: #333333; background-color: #ffffff; font-size: 14px;"&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DDR Stress Test (2.6.0)&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Build: Aug &amp;nbsp;1 2017, 17:33:18&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; NXP Semiconductors.&lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Chip ID&lt;/DIV&gt;&lt;DIV&gt;CHIP ID = i.MX6 Solo/DualLite (0x61)&lt;/DIV&gt;&lt;DIV&gt;Internal Revision = TO1.2&lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Boot Configuration&lt;/DIV&gt;&lt;DIV&gt;SRC_SBMR1(0x020d8004) = 0x00001040&lt;/DIV&gt;&lt;DIV&gt;SRC_SBMR2(0x020d801c) = 0x22000001&lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;ARM Clock set to 1GHz&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; DDR configuration&lt;/DIV&gt;&lt;DIV&gt;BOOT_CFG3[5-4]: 0x00, Single DDR channel.&lt;/DIV&gt;&lt;DIV&gt;DDR type is LPDDR2 in 1-channel mode.&lt;/DIV&gt;&lt;DIV&gt;Data width: 32, bank num: 8&lt;/DIV&gt;&lt;DIV&gt;Row size: 14, col size: 10&lt;/DIV&gt;&lt;DIV&gt;Both chip select CSD0 and CSD1 are used &amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Density per chip select: 512MB&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Density per channel: 1024MB&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Current Temperature: 59&lt;/DIV&gt;&lt;DIV&gt;============================================&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;DDR Freq: 396 MHz&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Note: Array result[] holds the DRAM test result of each byte. &amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; 0: test pass. &amp;nbsp;1: test fail &amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; 4 bits respresent the result of 1 byte. &amp;nbsp; &amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; result 0001:byte 0 fail.&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; result 0011:byte 0, 1 fail.&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Starting Read calibration...&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x00000000&lt;SPAN&gt; &lt;/SPAN&gt;result[00]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x04040404&lt;SPAN&gt; &lt;/SPAN&gt;result[01]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x08080808&lt;SPAN&gt; &lt;/SPAN&gt;result[02]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x0C0C0C0C&lt;SPAN&gt; &lt;/SPAN&gt;result[03]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x10101010&lt;SPAN&gt; &lt;/SPAN&gt;result[04]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x14141414&lt;SPAN&gt; &lt;/SPAN&gt;result[05]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x18181818&lt;SPAN&gt; &lt;/SPAN&gt;result[06]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x1C1C1C1C&lt;SPAN&gt; &lt;/SPAN&gt;result[07]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x20202020&lt;SPAN&gt; &lt;/SPAN&gt;result[08]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x24242424&lt;SPAN&gt; &lt;/SPAN&gt;result[09]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x28282828&lt;SPAN&gt; &lt;/SPAN&gt;result[0A]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x2C2C2C2C&lt;SPAN&gt; &lt;/SPAN&gt;result[0B]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x30303030&lt;SPAN&gt; &lt;/SPAN&gt;result[0C]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x34343434&lt;SPAN&gt; &lt;/SPAN&gt;result[0D]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x38383838&lt;SPAN&gt; &lt;/SPAN&gt;result[0E]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x3C3C3C3C&lt;SPAN&gt; &lt;/SPAN&gt;result[0F]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x40404040&lt;SPAN&gt; &lt;/SPAN&gt;result[10]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x44444444&lt;SPAN&gt; &lt;/SPAN&gt;result[11]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x48484848&lt;SPAN&gt; &lt;/SPAN&gt;result[12]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x4C4C4C4C&lt;SPAN&gt; &lt;/SPAN&gt;result[13]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x50505050&lt;SPAN&gt; &lt;/SPAN&gt;result[14]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x54545454&lt;SPAN&gt; &lt;/SPAN&gt;result[15]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x58585858&lt;SPAN&gt; &lt;/SPAN&gt;result[16]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x5C5C5C5C&lt;SPAN&gt; &lt;/SPAN&gt;result[17]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x60606060&lt;SPAN&gt; &lt;/SPAN&gt;result[18]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x64646464&lt;SPAN&gt; &lt;/SPAN&gt;result[19]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x68686868&lt;SPAN&gt; &lt;/SPAN&gt;result[1A]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x6C6C6C6C&lt;SPAN&gt; &lt;/SPAN&gt;result[1B]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x70707070&lt;SPAN&gt; &lt;/SPAN&gt;result[1C]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x74747474&lt;SPAN&gt; &lt;/SPAN&gt;result[1D]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x78787878&lt;SPAN&gt; &lt;/SPAN&gt;result[1E]=0x1111&lt;/DIV&gt;&lt;DIV&gt;ABS_OFFSET=0x7C7C7C7C&lt;SPAN&gt; &lt;/SPAN&gt;result[1F]=0x1111&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;ERROR FOUND, we can't get suitable value !!!!&lt;/DIV&gt;&lt;DIV&gt;dram test fails for all values.&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Error: failed during ddr calibration&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Best Regards.&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Aug 2017 03:09:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682199#M105405</guid>
      <dc:creator>zhanghaijian</dc:creator>
      <dc:date>2017-08-08T03:09:29Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6S + LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682200#M105406</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi zhang&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for error descriptions please check&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and FAQ section on:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-105652"&gt;i.MX6/7 DDR Stress Test Tool V2.70&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Aug 2017 10:43:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6S-LPDDR2/m-p/682200#M105406</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-08-08T10:43:23Z</dc:date>
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