i.MX ProcessorsのトピックRe: i.MX 6 ULL Layout and Stack up

i.MX 6 ULL Layout and Stack up

rbillen — Mon, 03 Jul 2017 11:01:11 GMT

I am designing a new product with the i/MX 6 ULL at the heart. I have the NXP design guidelines. They use a fairly large PCB as the basis with 4 layers, medium sized through hole vias and all surface routing for the DDR3. I have seen some PCB's with the DDR butted right up against the processor and I am under pressure from my boss to emulate this design. However, my solution would be 8 layers for good plane shielding and possibly blind/buried uVias, however, my boss is also keen to keep costs low, like penny pinchingly low. (His suggestion is no blind/buried and 6 layers). Any advice?

Re: i.MX 6 ULL Layout and Stack up

igorpadykov — Mon, 03 Jul 2017 23:18:23 GMT

Hi Robert

seems this solution is also possible only may be suggested to keep

routing for the DDR3 the same as it is done on i.MX6ULL EVK board.

Also may be recommended to keep power section, general rules are described in

Hardware Development Guide for the i.MX 6UltraLite Applications Processor

http://www.nxp.com/docs/en/user-guide/IMX6ULLHDG.pdf

Best regards
igor
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Re: i.MX 6 ULL Layout and Stack up

rbillen — Tue, 04 Jul 2017 08:15:07 GMT

I appreciate the reply Igor. I have got the Development guide already. Unfortunately, given the dimensions of the PCB that I am attempting to design I don't have the space to layout the DDR3 the same as the eval board, it has to be placed in line with the processor with very little room, similar to the Dart-6UL from Variscite (but I don't know how they have done it). I have routed more or less exactly as the eval board but there isn't any room for delay tuning and as a result I have blocked access to other pins on the i.MX 6.