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    <title>i.MX ProcessorsのトピックRe: spi2.0: Port 2: Possible RX FIFO overrun</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681561#M105280</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;To avoid the overrun issue, I used software flow control mechanism ( XON and&amp;nbsp;XOFF).&lt;/P&gt;&lt;P&gt;If both side has the software flow control, the issue is not observed.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 27 Jun 2017 08:00:46 GMT</pubDate>
    <dc:creator>surendradhobale</dc:creator>
    <dc:date>2017-06-27T08:00:46Z</dc:date>
    <item>
      <title>spi2.0: Port 2: Possible RX FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681559#M105278</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I have successfully interfaced the max14830 chip with imx6ul over spi. I am able to transreceiver the data on one of the RS485 ( UART/ ttyMAX2 ) port. With Loopback everything works fine.&lt;/P&gt;&lt;P&gt;Now when I am trying to send the data ( like 200 bytes or more ) from other device to /dev/ttyMAX2 port ( UART expander port). Getting the RX overrun error and loss the few data.&lt;/P&gt;&lt;P&gt;I have tried with different baud rate like 9600 or 115200 bps.Still same issue.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What could be the causes for the RX overrun ? How to be resolve ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Surendra&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Jun 2017 11:30:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681559#M105278</guid>
      <dc:creator>surendradhobale</dc:creator>
      <dc:date>2017-06-09T11:30:21Z</dc:date>
    </item>
    <item>
      <title>Re: spi2.0: Port 2: Possible RX FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681560#M105279</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Surendra&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;reason may be operating system latencies if there is&lt;/P&gt;&lt;P&gt;much graphics or video. One can test without os using&lt;/P&gt;&lt;P&gt;attached baremetal uart test (please refer to Chapter 33&lt;BR /&gt;Configuring the UART Driver pdf document), full sdk can be obtained&lt;/P&gt;&lt;P&gt;created service request. In operating system one can try to use uart&lt;/P&gt;&lt;P&gt;flow control to avoid overruns.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Jun 2017 22:57:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681560#M105279</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-06-09T22:57:38Z</dc:date>
    </item>
    <item>
      <title>Re: spi2.0: Port 2: Possible RX FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681561#M105280</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;To avoid the overrun issue, I used software flow control mechanism ( XON and&amp;nbsp;XOFF).&lt;/P&gt;&lt;P&gt;If both side has the software flow control, the issue is not observed.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Jun 2017 08:00:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi2-0-Port-2-Possible-RX-FIFO-overrun/m-p/681561#M105280</guid>
      <dc:creator>surendradhobale</dc:creator>
      <dc:date>2017-06-27T08:00:46Z</dc:date>
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