i.MX ProcessorsのトピックRe: How should the spread spectrum range be designed?

How should the spread spectrum range be designed?

t-iishii — Thu, 08 Jun 2017 08:05:44 GMT

Hello community,

Our customer plan to use spread spectrum for System PLL.

Target condition and register setting are following

Target :

Spread spectrum range = 3.52MHz （0.67% of 528MHz →ΔT=0.0126ns→0.5% of 396MHz）

Modulation frequency = 48kHz

Frequency change step = 14.08kHz

CCM_ANALOG_PLL_SYS_DENOM[B] = 0x0005B8D8 = 375000

CCM_ANALOG_PLL_SYS_SS[STOP] = 0xD6D8 = 55000

CCM_ANALOG_PLL_SYS_SS[STEP] = 0xDC = 220

CCM_ANALOG_PLL_SYS_SS[ENABLE] = 1b

System PLL condition :

PLL2 = 528MHz

PLL2-PFD0 = 500.21MHz

LDB-DI0 = 71.46MHz = 500.21MHz / 7

Attached figure are spectrum of LDB-DI0 output clock.

Before enable spread spectrum, IMG_0615.jpg

After enable spread spectrum, IMG_0619.jpg

In IMG_0619.jpg, it have three spectrum over 71.46MHz.

Why do spectra occur at high frequencies even though they are down spectrum?

Best regards,

Ishii.

Re: How should the spread spectrum range be designed?

art — Wed, 21 Jun 2017 11:23:57 GMT

Actually, this spread spectrum mechanism generates the pairs of symmetric spectral frequency harmonics (both upper and lower) around the center frequency of the frequency shift range, i.e. (initial frequency) minus (frequency shift range divided by two), or 71.46MHz - 3.52MHz/2 = 71.46 - 1.76 MHz = 69.7 MHz in your case. So, it's normal to observe the harmonics at the frequencies even upper than the initial one.

Have a great day,
Artur

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Re: How should the spread spectrum range be designed?

t-iishii — Fri, 23 Jun 2017 05:19:26 GMT

Hello Artur,

Thank you for your response.

I under stand that this spread spectrum will generate both upper and lower side harmonics.

I will ask it to my customer.

Best regards,

Ishii.