i.MX ProcessorsのトピックRe: i.MX6Q DDR clock

i.MX6Q DDR clock

sugiyamatoshihi — Fri, 30 Jun 2017 08:41:34 GMT

I read this thread, but I need more information.

i.MX6DQ SABRE SDP/B DDR3 Register Programming Aid

I 'd like to know how waveform change when CK_FT0_DCC and CK_FT1_DCC register value were changed.

Could you look at attached SDCLK_CK_FTx_DCC_.xlsx file?

1. Which case is correct CASE1 (red frame) or CASE2(green frame) when CK_FTx_DCC value changed?

2. As the reference manual description, CK_FT0_DCC is the primary and CK_FT1_DCC is secondary and it is cascaded. Does it means if both register value set 001(51.5% high each), then clock duty would be 53% high cycle? if it doesn't work like this, how it work when both register set 001 and 100?

Best Regards,

Sugiyama

Re: i.MX6Q DDR clock

gusarambula — Fri, 30 Jun 2017 23:32:01 GMT

Hello Toshihisa Sugiyama ,

Mark is definitely the right person to ask in this case. But in the meantime, there is a similar question and some information on the following thread:

https://community.nxp.com/message/624155?commentID=624155#comment-624155

Regards,

Re: i.MX6Q DDR clock

sugiyamatoshihi — Mon, 03 Jul 2017 00:18:22 GMT

Hi, gusarambla,

Thank you for your support.

I understood cascaded connection.

So, I 'd like to know which case is expected behavior when CK_FT0_DCC and CK_FT1_DCC register value were changed.

Best Regards,

Sugiyama

Re: i.MX6Q DDR clock

TheAdmiral — Fri, 07 Jul 2017 23:20:03 GMT

Hi Toshihisa-san,

I'm sorry for taking so long to answer your question.

From your spreadsheet, CASE 2 (Green) is correct. Maybe this physical description of what is happening will help:

The duty cycle adjustment is performed internal to the PHY, while the signal is still Single-Ended. The signal passes out of the PHY, to the Dual-DDR pad (special pad for differential pairs), where the Single-Ended signal is provided as an input to two buffer-gates in parallel: One buffer inverts the signal, and one buffer is non-interting. Since the duty cycle adjustment has already been applied, a setting of 001 will increase the duty cycle of the non-inverted signal by 1.5%, and will actuall decrease the inverted signal by 1.5%.

For your second question, yes, the two register effects are cascaded: the second cascade is applied after the first. They are cumulative, so that if both duty cycle controls are set to 001, the final adjust will increase the duty cycle to 53%. If one register is set to 001 and the other is set to 100, then the effects will cancel.

In practice, the actual change is applied by a fixed time delay of ~ 28 picoseconds on one of the clock edges, which will cause a 1.5% change at 528 MHz. The duty cycle change at 400 MHz will be closer to 1%.

Hope this clears this issue up for you.

Cheers,

Mark

Re: i.MX6Q DDR clock

sugiyamatoshihi — Tue, 11 Jul 2017 09:06:26 GMT

Hi, Mark,

Thank you for your answer. I understood.

it is very helpful.

Best Regards,

Sugiyama