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    <title>topic Re:  SAI transmit FIFO pointers in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679456#M104891</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; RFP bit field of I2Sx_TFRn shows how much elements have been really transferred &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;to an external (audio) device, assuming the device reads data from the i.MX6 FIFO. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;It is incremented once the data leave the FIFO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; WFP in a I2Sx_RFR shows how much elements have been really loaded from an external &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;(audio) device, assuming the device writes data to the i.MX6 FIFO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;It is incremented once the data is put to the receive FIFO. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 08 Jun 2017 07:40:57 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-06-08T07:40:57Z</dc:date>
    <item>
      <title>SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679455#M104890</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Again I came back to the FIFO fill level calculations for SAI. If it is not possible to get the tx/rx FIFO fill level so how it is possible to know it? Lets say SSI has got FIFO counter for that purpose. What can you suggest?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, could you at least give more brief description about WFP and RFP pointer values in case receive/transmit FIFO is not FULL? Let say receive/transmit FIFO is half full. Do the pointer values differ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Br,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Jun 2017 12:26:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679455#M104890</guid>
      <dc:creator>linasstaisiunas</dc:creator>
      <dc:date>2017-06-06T12:26:48Z</dc:date>
    </item>
    <item>
      <title>Re:  SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679456#M104891</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; RFP bit field of I2Sx_TFRn shows how much elements have been really transferred &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;to an external (audio) device, assuming the device reads data from the i.MX6 FIFO. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;It is incremented once the data leave the FIFO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; WFP in a I2Sx_RFR shows how much elements have been really loaded from an external &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;(audio) device, assuming the device writes data to the i.MX6 FIFO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;It is incremented once the data is put to the receive FIFO. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Jun 2017 07:40:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679456#M104891</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-08T07:40:57Z</dc:date>
    </item>
    <item>
      <title>Re:  SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679457#M104892</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Ok. That is clear. Another question related to fifo pointers. For example I got SAI transmit interrupt based on FIFO watermark configuration. This means that there are still left data in a TX FIFO. I want to use I2Sx_TFRn fields RFP and WFP to calculate transmit FIFO free space. Is it the correct way to do it? When in a transmit interrupt I don't want to put too much data to TDR register. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Br,&lt;/P&gt;&lt;P&gt;Linas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Jun 2017 08:23:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679457#M104892</guid>
      <dc:creator>linasstaisiunas</dc:creator>
      <dc:date>2017-06-09T08:23:26Z</dc:date>
    </item>
    <item>
      <title>Re:  SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679458#M104893</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; generally Your approach is possible. Some issue may take place, when FIFO&lt;/P&gt;&lt;P&gt;pointers change during interrupt serving. Therefore it makes sense to work with&lt;/P&gt;&lt;P&gt;fixed (size) block of data, say - half of FIFO to avoid FIFO under / over flow. &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Jun 2017 07:47:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/679458#M104893</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-21T07:47:09Z</dc:date>
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