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    <title>topic Re: i.mx6q plus uart FIFO overrun in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678949#M104829</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;Hi&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;igorpadykov&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;How to change the uart access priority through NIC&amp;amp;NOC?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN style="background-color: #ffffff; border: 0px; color: #51626f; font-weight: inherit; font-size: 18.004px;"&gt;The uart is connect to AIPS_TZ1.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN style="background-color: #ffffff; border: 0px; color: #51626f; font-weight: inherit; font-size: 18.004px;"&gt;I search the technical reference manual,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;But there is no any describe on NIC&amp;amp;NOC about&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;AIPS_TZ1.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 08 Aug 2017 08:56:07 GMT</pubDate>
    <dc:creator>linya</dc:creator>
    <dc:date>2017-08-08T08:56:07Z</dc:date>
    <item>
      <title>i.mx6q plus uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678947#M104827</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I migrant cpu from i.mx6q to i.mx6 plus.&lt;/P&gt;&lt;P&gt;the software is yocto imx_3.14.52_1.1.0_ga&lt;/P&gt;&lt;P&gt;I test the same software, except device tree file, on both platform.&lt;/P&gt;&lt;P&gt;The same rootfs and zImage,&amp;nbsp; different device tree file with the same uart config.&lt;/P&gt;&lt;P&gt;on i.mx6q the uart run well but i.mx6q plus encounter uart fifo overrun.&lt;/P&gt;&lt;P&gt;the message is like bellow:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[ 424.287781] imx-uart 21ec000.serial: Rx FIFO overrun&lt;BR /&gt;[ 425.287739] imx-uart 21ec000.serial: Rx FIFO overrun&lt;BR /&gt;[ 426.287685] imx-uart 21ec000.serial: Rx FIFO overrun&lt;BR /&gt;[ 427.287632] imx-uart 21ec000.serial: Rx FIFO overrun&lt;BR /&gt;[ 428.287580] imx-uart 21ec000.serial: Rx FIFO overrun&lt;BR /&gt;[ 429.287530] imx-uart 21ec000.serial: Rx FIFO overrun&lt;BR /&gt;[ 430.287476] imx-uart 21ec000.serial: Rx FIFO overrun&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I check the message:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/382099"&gt;iMX6Quad uart RX Fifo Overrun&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My overall bus load is 78% on i.mx6q,&lt;/P&gt;&lt;P&gt;But i.mx6q plus is just 43%, it far bellow i.mx6q.&lt;/P&gt;&lt;P&gt;This is no look like bus load issue.&lt;/P&gt;&lt;P&gt;What is root cause ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;MMDC new Profiling results:&lt;BR /&gt;***********************&lt;BR /&gt;Measure time: 500ms &lt;BR /&gt;Total cycles count: 264066104&lt;BR /&gt;Busy cycles count: 114651213&lt;BR /&gt;Read accesses count: 8899358&lt;BR /&gt;Write accesses count: 6043767&lt;BR /&gt;Read bytes count: 422906320&lt;BR /&gt;Write bytes count: 266389076&lt;BR /&gt;Avg. Read burst size: 47&lt;BR /&gt;Avg. Write burst size: 44&lt;BR /&gt;Read: 806.63 MB/s / Write: 508.10 MB/s Total: 1314.73 MB/s &lt;BR /&gt;Utilization: 37%&lt;BR /&gt;Overall Bus Load: 43%&lt;BR /&gt;Bytes Access: 46&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I try to change the uart Qos.&lt;/P&gt;&lt;P&gt;The uart is connect to AIPS_TZ1.&lt;/P&gt;&lt;P&gt;I check the applications processor reference manual chapter 47.3.4&amp;nbsp; NIC-specific parameters&lt;/P&gt;&lt;P&gt;But there is no AIPS on table 47-5&lt;/P&gt;&lt;P&gt;How can I change the Qos for uart?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Jul 2017 08:35:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678947#M104827</guid>
      <dc:creator>linya</dc:creator>
      <dc:date>2017-07-24T08:35:34Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6q plus uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678948#M104828</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi lin&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;reason may be delays produced by bus arbiters (NIC&amp;amp;NOC described in&lt;/P&gt;&lt;P&gt;Chapter 47 Network Interconnect Bus System). General solution is to use&lt;/P&gt;&lt;P&gt;hardware flow control support with rts,cts signals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Jul 2017 10:59:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678948#M104828</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-07-24T10:59:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6q plus uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678949#M104829</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;Hi&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;igorpadykov&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;How to change the uart access priority through NIC&amp;amp;NOC?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN style="background-color: #ffffff; border: 0px; color: #51626f; font-weight: inherit; font-size: 18.004px;"&gt;The uart is connect to AIPS_TZ1.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN style="background-color: #ffffff; border: 0px; color: #51626f; font-weight: inherit; font-size: 18.004px;"&gt;I search the technical reference manual,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;But there is no any describe on NIC&amp;amp;NOC about&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;AIPS_TZ1.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Aug 2017 08:56:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678949#M104829</guid>
      <dc:creator>linya</dc:creator>
      <dc:date>2017-08-08T08:56:07Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6q plus uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678950#M104830</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;example to set enet priority to 3 :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/unit_tests/memtool -32 0x00247100=0x3&lt;BR /&gt;/unit_tests/memtool -32 0x00247104=0x3&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;refer to i.MX6DQ reference manual Table 45-5. QoS and tidemark parameters.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Aug 2017 10:50:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678950#M104830</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-08-08T10:50:01Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6q plus uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678951#M104831</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN class=""&gt;&lt;A _jive_internal="true" data-content-finding="Community" data-userid="206296" data-username="igorpadykov" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am not able to find the uart or aips_tz1 item from i.MX6DQ reference manual Table 45-5.&lt;/P&gt;&lt;P&gt;Which item is relate to uart in Table 45-5?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Aug 2017 03:44:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678951#M104831</guid>
      <dc:creator>linya</dc:creator>
      <dc:date>2017-08-09T03:44:14Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6q plus uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678952#M104832</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN class=""&gt;&lt;A _jive_internal="true" data-containerid="-1" data-containertype="-1" data-content-finding="Community" data-objectid="206296" data-objecttype="3" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This issue happen after run 3D test case S07_EnvironmentMapping_FB&lt;/P&gt;&lt;P&gt;connect ttymxc2 with 115200 bit rate data source&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.&amp;nbsp;&amp;nbsp; cat /dev/ttymxc2 &amp;amp;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;&amp;nbsp; S07_EnvironmentMapping_FB&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;my urat config is:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;uart3 {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;pinctrl-names = "default";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_uart3&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;pinctrl_uart3: uart3grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1&lt;BR /&gt; MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Oct 2017 11:13:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6q-plus-uart-FIFO-overrun/m-p/678952#M104832</guid>
      <dc:creator>linya</dc:creator>
      <dc:date>2017-10-10T11:13:09Z</dc:date>
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