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    <title>i.MX Processors中的主题 iMX286 custom board: need some hints.</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX286-custom-board-need-some-hints/m-p/196436#M10464</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I've just beginning to design a iMX286 custom board taking as reference the EVK schematics and layout. I hope someone with previous experience in this matter can give some hints about:&lt;BR /&gt; &lt;BR /&gt; 1. I will use: 2xUSB, 1xETH, 2xCAN, 24bit LCD and 8xGPIO. With this amount of nets and using 4 layer, 4mil track/space and 8mil/16mil vias I can do the fanout without problems. However I still concerned about the convenience or not to use 6L and so to fill a layer only with power planes. Have any of you manufactured a 4L board without EMC problems?&lt;BR /&gt; &lt;BR /&gt; 2. I can see DDR EMI_A13 and EMI_A14 nets connected in the EVK schematics. Why? The memory has 1Gb not 4Gb... Besides I can see those pins as NC&amp;nbsp; on the EDE1116AEBG datasheet.&lt;BR /&gt; &lt;BR /&gt; 3.&amp;nbsp; How do I place the DDR decoupling capacitors?. There are 16 power pins (VDD, VDDQ and VDDL) and I can see 13 capacitors with different values (0.01, 0.1, 0.22 and 10uF). I really don't know how to link them.&lt;BR /&gt; &lt;BR /&gt; Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 18 Dec 2011 12:51:38 GMT</pubDate>
    <dc:creator>ManuMartinez</dc:creator>
    <dc:date>2011-12-18T12:51:38Z</dc:date>
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      <title>iMX286 custom board: need some hints.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX286-custom-board-need-some-hints/m-p/196436#M10464</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I've just beginning to design a iMX286 custom board taking as reference the EVK schematics and layout. I hope someone with previous experience in this matter can give some hints about:&lt;BR /&gt; &lt;BR /&gt; 1. I will use: 2xUSB, 1xETH, 2xCAN, 24bit LCD and 8xGPIO. With this amount of nets and using 4 layer, 4mil track/space and 8mil/16mil vias I can do the fanout without problems. However I still concerned about the convenience or not to use 6L and so to fill a layer only with power planes. Have any of you manufactured a 4L board without EMC problems?&lt;BR /&gt; &lt;BR /&gt; 2. I can see DDR EMI_A13 and EMI_A14 nets connected in the EVK schematics. Why? The memory has 1Gb not 4Gb... Besides I can see those pins as NC&amp;nbsp; on the EDE1116AEBG datasheet.&lt;BR /&gt; &lt;BR /&gt; 3.&amp;nbsp; How do I place the DDR decoupling capacitors?. There are 16 power pins (VDD, VDDQ and VDDL) and I can see 13 capacitors with different values (0.01, 0.1, 0.22 and 10uF). I really don't know how to link them.&lt;BR /&gt; &lt;BR /&gt; Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 18 Dec 2011 12:51:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX286-custom-board-need-some-hints/m-p/196436#M10464</guid>
      <dc:creator>ManuMartinez</dc:creator>
      <dc:date>2011-12-18T12:51:38Z</dc:date>
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