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    <title>topic Re: EIM write and read Turn around time Issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678067#M104636</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Artur,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this turnaround time coming into play when performing a because Udaya seems to&amp;nbsp; be doing alternate Write and &amp;nbsp;Read?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What if I am doing consecutive Writes? I am facing a similar issue, I am using a 16 bit multiplexed Asynchronous mode. And from my code I am writing 32 bytes of data in a for loop. I am using iMX51 though but I guess the symptom is the same. Here is my WEIM CS0 configuration:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;{ &lt;BR /&gt; 0x00010039 , //CSxGCR1&lt;BR /&gt; 0x00000002 , //CSxGCR2&lt;BR /&gt; 0x20475230 , //CSxRCR1&lt;BR /&gt; 0x00000000 , //CSxRCR2&lt;BR /&gt; 0x609C0E98 , //CSxWCR1&lt;BR /&gt; 0x00000000 , //CSxWCR2&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am able to increase/decrease the CS timing using CS0WCR1.WWSC but the delay in between two consecutive chip selects is of the order of 200nanoSecs, even though I have set CS0GCR1.CSREC to 0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The rate at which I can send data out on the WEIM Bus is very critical, can you please suggest me a way in which the inter-CS time can be brought down? Is Burst mode synchronous access going to result in faster data throughput?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 19 Jan 2018 13:43:40 GMT</pubDate>
    <dc:creator>DeepakKukreja</dc:creator>
    <dc:date>2018-01-19T13:43:40Z</dc:date>
    <item>
      <title>EIM write and read Turn around time Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678065#M104634</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; We use EIM to write and read a SRAM in asynchronous mode ,where i could able to read and write with the configuration below in IMX6Q.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;EIM_CS0GCR1 = 0x00010081&lt;/P&gt;&lt;P&gt;EIM_CS0GCR2 = 0x00000000&lt;/P&gt;&lt;P&gt;EIM_CS0RCR1 = 0x04000000&lt;/P&gt;&lt;P&gt;EIM_CS0RCR2 = 0x00000000&lt;/P&gt;&lt;P&gt;EIM_CS0WCR1= 0x04000000&lt;/P&gt;&lt;P&gt;EIM_CS0WCR2= 0x00000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;where read and write able to do in 30 ns and the turn around time in between is 270 ns.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="read_write1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/25325i0232B08FCE5A73A1/image-size/large?v=v2&amp;amp;px=999" role="button" title="read_write1.png" alt="read_write1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. I need to reduce the turn around time less than 40 ns could it be acheivable ?&lt;/P&gt;&lt;P&gt;2. where I need to change the configuration and things to taken care to acheive write and read with turn around time less than 100 ns?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks in advance ..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;uday&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jun 2017 06:26:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678065#M104634</guid>
      <dc:creator>udayakumar</dc:creator>
      <dc:date>2017-06-29T06:26:19Z</dc:date>
    </item>
    <item>
      <title>Re: EIM write and read Turn around time Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678066#M104635</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Your current EIM setup already implements the fastest turnaround time of the accesses. So, most likely, the large gaps between the accesses are caused by the processor's internal buses arbitration timings and cannot be improved.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Jun 2017 06:39:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678066#M104635</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2017-06-30T06:39:23Z</dc:date>
    </item>
    <item>
      <title>Re: EIM write and read Turn around time Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678067#M104636</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Artur,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this turnaround time coming into play when performing a because Udaya seems to&amp;nbsp; be doing alternate Write and &amp;nbsp;Read?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What if I am doing consecutive Writes? I am facing a similar issue, I am using a 16 bit multiplexed Asynchronous mode. And from my code I am writing 32 bytes of data in a for loop. I am using iMX51 though but I guess the symptom is the same. Here is my WEIM CS0 configuration:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;{ &lt;BR /&gt; 0x00010039 , //CSxGCR1&lt;BR /&gt; 0x00000002 , //CSxGCR2&lt;BR /&gt; 0x20475230 , //CSxRCR1&lt;BR /&gt; 0x00000000 , //CSxRCR2&lt;BR /&gt; 0x609C0E98 , //CSxWCR1&lt;BR /&gt; 0x00000000 , //CSxWCR2&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am able to increase/decrease the CS timing using CS0WCR1.WWSC but the delay in between two consecutive chip selects is of the order of 200nanoSecs, even though I have set CS0GCR1.CSREC to 0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The rate at which I can send data out on the WEIM Bus is very critical, can you please suggest me a way in which the inter-CS time can be brought down? Is Burst mode synchronous access going to result in faster data throughput?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 19 Jan 2018 13:43:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678067#M104636</guid>
      <dc:creator>DeepakKukreja</dc:creator>
      <dc:date>2018-01-19T13:43:40Z</dc:date>
    </item>
    <item>
      <title>Re: EIM write and read Turn around time Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678068#M104637</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i use EIM bus in&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;asynchronous mode,the real &lt;SPAN&gt;throughput&lt;/SPAN&gt; is just like yours result,i think if use&amp;nbsp;&lt;SPAN&gt;Burst mode synchronous will be better.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 20 Jan 2018 01:55:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-write-and-read-Turn-around-time-Issue/m-p/678068#M104637</guid>
      <dc:creator>吴智吴智</dc:creator>
      <dc:date>2018-01-20T01:55:40Z</dc:date>
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