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    <title>i.MX ProcessorsのトピックQuestion, i.MX6UltraLight ERR010690</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676496#M104344</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about ERR010690, SNVS_LP registers reset issue, of i.MX6UL.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer is using i.MX6UL Rev.1.1 chips.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And they have a concern on ERR010690.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;They have questions on ERR010690 as below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Please give your answers to the following questions.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The power supply circuitry of their board is similar as your EVK board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can this issue mentioned in ERR010690 occur also on your EVK?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(2)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The customer is using SRTC backup by coin-cell.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In the description of ERR010690, the registers of SNVS_LP is not specified.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is mentioned only as ‘SNVS_LP registers’.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you give the details about exactly what registers can be affected by this issue?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;They want to know whether it is possible to affect their SRTC backup feature.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 06 Jun 2017 06:00:26 GMT</pubDate>
    <dc:creator>SLICE</dc:creator>
    <dc:date>2017-06-06T06:00:26Z</dc:date>
    <item>
      <title>Question, i.MX6UltraLight ERR010690</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676496#M104344</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about ERR010690, SNVS_LP registers reset issue, of i.MX6UL.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer is using i.MX6UL Rev.1.1 chips.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And they have a concern on ERR010690.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;They have questions on ERR010690 as below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Please give your answers to the following questions.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The power supply circuitry of their board is similar as your EVK board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can this issue mentioned in ERR010690 occur also on your EVK?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(2)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The customer is using SRTC backup by coin-cell.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In the description of ERR010690, the registers of SNVS_LP is not specified.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is mentioned only as ‘SNVS_LP registers’.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you give the details about exactly what registers can be affected by this issue?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;They want to know whether it is possible to affect their SRTC backup feature.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Jun 2017 06:00:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676496#M104344</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-06-06T06:00:26Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6UltraLight ERR010690</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676497#M104345</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; On the EVK scheme :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;VDD_ARM_SOC_IN is controlled by DCDC_3V3_PG (3.3V is good), &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;but VDD_HIGH_IN is connected directly to DCDC_3V3. This means :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;VDD_SOC_IN is ramping up when VDD_HIGH_IN is not higher than 3.0 V.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;VDD_SOC_IN is ramping down when VDD_HIGH_IN is lower than 3.0 V. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;VDD_SOC_IN is not ramping down earlier than VDD_HIGH_IN.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; So, the EVK should not be affected with the erratum. But the Errata recommends the following :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The workarounds below should be both used to avoid SNVS_LP registers reset issue:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;• VDD_HIGH_IN power down is earlier than VDD_SOC_IN.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;• VDD_HIGH_IN voltage power is less than or equal to 3.0 V. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The second item is not satisfied on the EVK.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; All registers inside SNVS_LP may be reset. Please look at section 46.7.1 (SNVS Memory Map) of i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1, 04/2016.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Jun 2017 07:54:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676497#M104345</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-06T07:54:25Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6UltraLight ERR010690</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676498#M104346</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;That is;&lt;/P&gt;&lt;P&gt;1.&lt;/P&gt;&lt;P&gt;This issue can be occur even on EVK.&lt;/P&gt;&lt;P&gt;2.&lt;/P&gt;&lt;P&gt;RTC also can be lost if the issue occur.&lt;/P&gt;&lt;P&gt;Right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Jun 2017 09:13:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676498#M104346</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-06-06T09:13:34Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6UltraLight ERR010690</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676499#M104347</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; yes, You are right. &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Jun 2017 06:17:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6UltraLight-ERR010690/m-p/676499#M104347</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-09T06:17:05Z</dc:date>
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