topic Re: i.MX6 Solo DDR Controller question in i.MX Processors

i.MX6 Solo DDR Controller question

wenbinxu — Mon, 05 Jun 2017 02:08:43 GMT

Hello, i have a project using i.MX6 Solo as the CPU of system, and as the portable device we want to use LP-DDR2 instead of DDR3 for power consumption optimization, but the datasheet says there is a pin mux mapping for LP-DDR2 and DDR3. When i found it in the reference manual Table 45-7, it seems a kind of strange. the address bus and other control signals in the pin mux mapping are blended together, for exemple DRAM-ADDR09 in mode DDR3 correspond to LPDDR2_CKE1_P1 in mode LP-DDR2. So i wish to receive your confirmation and explanation of this pin mux mapping, thank you.

Re: i.MX6 Solo DDR Controller question

Yuri — Tue, 06 Jun 2017 06:10:24 GMT

Hello,

LPDDR2 devices differ from DDR3 even on pin interface level, therefore on i.MX6 LPDDR2 and

DDR3 pin mux mapping was implemented.

You may look at LPDDR2 specs :

https://www.jedec.org/sites/default/files/docs/JESD209-2B.pdf

Have a great day,
Yuri

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Re: i.MX6 Solo DDR Controller question

wenbinxu — Tue, 06 Jun 2017 06:44:01 GMT

Thanks for your response Yuri, as you said that the interface level between LPDDR2 and DDR3 is quite different, but the DDR pin mux mapping of the i.MX6 Solo Lite serie is far more coherent than other series of i.MX6, that why i thought it is strange.