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    <title>topic Re: UART1 transmit on both TX and RX?! help on setup RX correctly in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674437#M103958</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Pablo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes i.MX6Q can transmit on both TX and RX, though not simultaneously,&lt;/P&gt;&lt;P&gt;please check Table 90. UART I/O Configuration vs. Mode i.MX6DQ Datasheet&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;For uart baremetal example please look at attached example from sdk and description in&lt;/P&gt;&lt;P&gt;Chapter 33 Configuring the UART Driver pdf document.&lt;/P&gt;&lt;P&gt;Full sdk can be obtained creating service request :&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fcommunity.freescale.com%2Fdocs%2FDOC-329745" rel="nofollow" target="_blank"&gt;https://community.freescale.com/docs/DOC-329745&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 26 Jun 2017 23:57:24 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-06-26T23:57:24Z</dc:date>
    <item>
      <title>UART1 transmit on both TX and RX?! help on setup RX correctly</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674436#M103957</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using iMX6Q UART with a RTOS. I started to notice a problem on the RX line and after some investigation I built a test code to be loaded with the JTAG or USB.&lt;/P&gt;&lt;P&gt;The test code initializes the UART1 at pin SD3_DATA6 (E13) as&amp;nbsp;ALT1 and pin SD3_DATA7 (F13) as ALT1&lt;/P&gt;&lt;P&gt;When I transmit some data I can see the electrical signal in the RX pin like the TX and RX line were connected together in a short circuit. I removed the HW peripheral circuit so my reading is at the pad level without anything connected, not even pull-ups or protection diodes. The TX and RX pins are &lt;STRONG&gt;not&lt;/STRONG&gt; shorted together, when device is powered off I measure &amp;gt;10Mohms.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Originally the defect when connected to a peripheral was showing collision (I mean the signal is visibly corrupted)&amp;nbsp;on RX pin only, but not on TX pin, so the pin is driven separately by iMX6 on both pins.&lt;/P&gt;&lt;P&gt;I decided to change the RX configuration to GPIO (ALT5) and I still see the signal :smileyshocked:. So at this point I thought the iMX6 could be damaged and I tried the test on another devices, all of them have the same problem even devices never powered up before and that were never running defective software drivers that could have damaged the HW.&lt;/P&gt;&lt;P&gt;At this point I tried to play a bit with the UART1 and IOMUX. I read the manual and checked all the bits, especially the DTE / DCE modes and loopback modes, but I couldn't make the RX pin to work as input only. I checked on internet and errata sheets and I got no matching problems.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Since it looks like I am the only one having this problem I decided I need help as I am definitely missing something.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here is the code:&lt;/P&gt;&lt;P&gt;it requires regsiomuxc.h regsccm.h regsgpio.h from the SDK&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#include &amp;lt;stdint.h&amp;gt;&lt;BR /&gt;#include "registers\regsiomuxc.h"&lt;BR /&gt;#include "registers\regsccm.h"&lt;BR /&gt;#include "registers/regsgpio.h"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define UART1&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;0x02020000&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define URXD&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x00))&amp;nbsp; // Receiver Register &lt;BR /&gt;#define UTXD&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x40)) // Transmitter Register &lt;BR /&gt;#define UCR1&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x80)) // Control Register 1 &lt;BR /&gt;#define UCR2&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x84)) // Control Register 2 &lt;BR /&gt;#define UCR3&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x88)) // Control Register 3 &lt;BR /&gt;#define UCR4&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x8c)) // Control Register 4 &lt;BR /&gt;#define UFCR&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x90)) // FIFO Control Register &lt;BR /&gt;#define USR1&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x94)) // Status Register 1 &lt;BR /&gt;#define USR2&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x98)) // Status Register 2 &lt;BR /&gt;#define UESC&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0x9c)) // Escape Character Register &lt;BR /&gt;#define UTIM&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0xa0)) // Escape Timer Register &lt;BR /&gt;#define UBIR&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0xa4)) // BRM Incremental Register &lt;BR /&gt;#define UBMR&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0xa8)) // BRM Modulator Register &lt;BR /&gt;#define UBRC&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0xac)) // Baud Rate Count Register &lt;BR /&gt;#define ONEMS&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0xb0)) // One Millisecond register &lt;BR /&gt;#define UTS&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;*((volatile uint32_t*)(((uint32_t)UART1) + 0xb4)) // UART Test Register on all other i.mx&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;void main(void)&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_CCM_CCGR0_WR(0xF0C03F0F);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_CCM_CCGR1_WR(0xF0FC0C00);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_CCM_CCGR2_WR(0xFC3FF00C);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_CCM_CCGR3_WR(0x3FF00000);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_CCM_CCGR4_WR(0x0000FF00);&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;HW_CCM_CCGR5_WR(0xF0033F0F | 0x0F000000&amp;nbsp;&amp;nbsp; );&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_CCM_CCGR6_WR(0xFFFF0303);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UCR1 = 0x00000000;&amp;nbsp;&amp;nbsp;&amp;nbsp; // power off UART&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Config pad SD3_DATA6(E13)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_V(DISABLED) | &amp;nbsp;&amp;nbsp; //tried both enabled disable, it does not change&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_V(&lt;STRONG&gt;ALT1&lt;/STRONG&gt;));&amp;nbsp;&amp;nbsp; //if I set to ALT5-input the RX is still being driven by TX driver&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_V(ENABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_V(100K_OHM_PU) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_V(PULL) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_V(ENABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_V(DISABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_V(100MHZ) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_V(40_OHM) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_V(SLOW));&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Config pad SD3_DATA7(F13)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_V(DISABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_V(&lt;STRONG&gt;ALT1&lt;/STRONG&gt;));&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_V(ENABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_V(100K_OHM_PU) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_V(PULL) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_V(ENABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_V(DISABLED) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_V(100MHZ) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_V(40_OHM) | &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_V(SLOW));&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_WR(&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; BF_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY_V(SD3_DATA6_ALT1)); // tried to change this bit in many ways, but still no luck&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;// tried to play with uart registers, everything looks right to me&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UCR2 = 0x00004027;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UCR3 = 0x00000784;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UCR4 = 0x00008000;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UESC = 0x0000002B;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UTIM = 0x00000000;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UTS&amp;nbsp; = 0x00000000;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UFCR = 0x00000001&amp;nbsp; | (4&amp;lt;&amp;lt;7);&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UBIR&amp;nbsp; = 12 - 1;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UBMR = 625 - 1;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;ONEMS = 16000000/(2 * 1000);&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;UCR1 = 0x00000001;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;for(;;)&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; while (UTS &amp;amp; (1&amp;lt;&amp;lt;4)); UTXD = (0x5A);&amp;nbsp;&amp;nbsp; // here i see the same signal on both TX and RX&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your help and suggestions! &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Jun 2017 17:47:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674436#M103957</guid>
      <dc:creator>pablosocolovsky</dc:creator>
      <dc:date>2017-06-26T17:47:40Z</dc:date>
    </item>
    <item>
      <title>Re: UART1 transmit on both TX and RX?! help on setup RX correctly</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674437#M103958</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Pablo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes i.MX6Q can transmit on both TX and RX, though not simultaneously,&lt;/P&gt;&lt;P&gt;please check Table 90. UART I/O Configuration vs. Mode i.MX6DQ Datasheet&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;For uart baremetal example please look at attached example from sdk and description in&lt;/P&gt;&lt;P&gt;Chapter 33 Configuring the UART Driver pdf document.&lt;/P&gt;&lt;P&gt;Full sdk can be obtained creating service request :&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fcommunity.freescale.com%2Fdocs%2FDOC-329745" rel="nofollow" target="_blank"&gt;https://community.freescale.com/docs/DOC-329745&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Jun 2017 23:57:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674437#M103958</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-06-26T23:57:24Z</dc:date>
    </item>
    <item>
      <title>Re: UART1 transmit on both TX and RX?! help on setup RX correctly</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674438#M103959</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I found the problem and is an HW problem. The SW used was fine. Thank you anyway for the suggestion.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Jun 2017 11:34:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART1-transmit-on-both-TX-and-RX-help-on-setup-RX-correctly/m-p/674438#M103959</guid>
      <dc:creator>pablosocolovsky</dc:creator>
      <dc:date>2017-06-27T11:34:41Z</dc:date>
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