<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックQuestion, i.MX6SX eMMC boot - SD port selection</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673249#M103740</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about eMMC boot of i.MX6SX.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In reference manual of i.MX6SX(IMX6SXRM, Rev.1), the following description is written in Table-5-6.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(For port selection) “eSDHC3 (eMMC4.4)”&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(For the other SDx ports, there is no written of "(eMMXx.x)".)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could show me the details of the description?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Should user use SD3 in the case of using eMMC4.4 device?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 02 Jun 2017 04:30:48 GMT</pubDate>
    <dc:creator>SLICE</dc:creator>
    <dc:date>2017-06-02T04:30:48Z</dc:date>
    <item>
      <title>Question, i.MX6SX eMMC boot - SD port selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673249#M103740</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about eMMC boot of i.MX6SX.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In reference manual of i.MX6SX(IMX6SXRM, Rev.1), the following description is written in Table-5-6.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(For port selection) “eSDHC3 (eMMC4.4)”&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(For the other SDx ports, there is no written of "(eMMXx.x)".)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could show me the details of the description?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Should user use SD3 in the case of using eMMC4.4 device?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 04:30:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673249#M103740</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-06-02T04:30:48Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot - SD port selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673250#M103741</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Basically there are no differences in uSDHC ports of i.MX6SX. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;From Table 2 (i.MX 6SoloX Modules List) of i.MX6SXDataSheet(s).&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;They are:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Fully compliant with MMC command/response sets and Physical Layer as defined &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;in the Multimedia Card System Specification, v4.5/4.2/4.3/4.4/4.41/ including&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;high-capacity (size &amp;gt; 2 GB) cards HC MMC.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Fully compliant with SD command/response sets and Physical Layer as defined in the &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SD Memory Card Specifications, v3.0 including high-capacity SDHC cards up to 32 GB.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Fully compliant with SDIO command/response sets and interrupt/read-wait mode as &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;defined in the SDIO Card Specification, Part E1, v3.0. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Conforms to the SD Host Controller StandardSpecification version 3.0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;All four ports support:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max) &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SDR and DDR modes (104 MB/s max)&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;All ports can work with 1.8 V and 3.3 V cards. Each port is placed on a separate power domain. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;It makes sense to follow NXP referenece design(s) if software compatibility with NXP BSPs&amp;nbsp; is needed. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 06:37:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673250#M103741</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-02T06:37:41Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot - SD port selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673251#M103742</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks for your kindly explanation.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But I still do not understand why NXP wrote it, ”(eMMC4.4)”, in “Port Select” in Table 5-6.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 06:54:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673251#M103742</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-06-02T06:54:55Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot - SD port selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673252#M103743</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Looks like as misprint.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 07:11:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673252#M103743</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-02T07:11:22Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot - SD port selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673253#M103744</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks! I will ignore it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 07:15:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot-SD-port-selection/m-p/673253#M103744</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-06-02T07:15:21Z</dc:date>
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  </channel>
</rss>

