topic How to control MIPI PHY power supply in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/How-to-control-MIPI-PHY-power-supply/m-p/672724#M103637 <HTML><HEAD></HEAD><BODY><P>Hi all</P><P></P><P></P><P>I want to know how to control MIPI PHY power. supply.</P><P>I'm using i.MX7D and have a custom board.</P><P></P><P>Q1.</P><P>How can I powered off the&nbsp;VDDA_PHY_1P8 ?</P><P>According to the P483 and 484 of RM,&nbsp;SW_PHY_1P8 seem to be able to power off.</P><P>Also the power rail of VDDA_1P8_IN has a switch in figure&nbsp;5-9. (Please see the following blue circle I pointer out.)&nbsp;</P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/20624iCC49473109E9D88D/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P></P><P>As a result, it must be have register to ON/OFF the VDDA_PHY_1P8.</P><P>Could you tell me which register can control the&nbsp;<SPAN>VDDA_PHY_1P8 ?</SPAN></P><P></P><P></P><P><SPAN>Q2</SPAN></P><P><SPAN>Is there any way to put CPU in Deep Sleep mode with keeping LP11 ?</SPAN></P><P>Currently, if you set the CPU to Deep Sleep, the MIPI D - PHY lane will be fixed to 0V.</P><P></P><P>Q3</P><P>Also, can you maintain D-PHY LP11 with VDDA_MIPI_1P0 dropped?</P><P></P><P></P><P>I would like to put the MIPI D-PHY in the state of LP11 (MIPI standby) to the state of low power consumption on the CPU side.</P><P></P><P></P><P>Ko-hey</P></BODY></HTML> Fri, 02 Jun 2017 07:42:52 GMT ko-hey 2017-06-02T07:42:52Z How to control MIPI PHY power supply https://community.nxp.com/t5/i-MX-Processors/How-to-control-MIPI-PHY-power-supply/m-p/672724#M103637 <HTML><HEAD></HEAD><BODY><P>Hi all</P><P></P><P></P><P>I want to know how to control MIPI PHY power. supply.</P><P>I'm using i.MX7D and have a custom board.</P><P></P><P>Q1.</P><P>How can I powered off the&nbsp;VDDA_PHY_1P8 ?</P><P>According to the P483 and 484 of RM,&nbsp;SW_PHY_1P8 seem to be able to power off.</P><P>Also the power rail of VDDA_1P8_IN has a switch in figure&nbsp;5-9. (Please see the following blue circle I pointer out.)&nbsp;</P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/20624iCC49473109E9D88D/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P></P><P>As a result, it must be have register to ON/OFF the VDDA_PHY_1P8.</P><P>Could you tell me which register can control the&nbsp;<SPAN>VDDA_PHY_1P8 ?</SPAN></P><P></P><P></P><P><SPAN>Q2</SPAN></P><P><SPAN>Is there any way to put CPU in Deep Sleep mode with keeping LP11 ?</SPAN></P><P>Currently, if you set the CPU to Deep Sleep, the MIPI D - PHY lane will be fixed to 0V.</P><P></P><P>Q3</P><P>Also, can you maintain D-PHY LP11 with VDDA_MIPI_1P0 dropped?</P><P></P><P></P><P>I would like to put the MIPI D-PHY in the state of LP11 (MIPI standby) to the state of low power consumption on the CPU side.</P><P></P><P></P><P>Ko-hey</P></BODY></HTML> Fri, 02 Jun 2017 07:42:52 GMT https://community.nxp.com/t5/i-MX-Processors/How-to-control-MIPI-PHY-power-supply/m-p/672724#M103637 ko-hey 2017-06-02T07:42:52Z Re: How to control MIPI PHY power supply https://community.nxp.com/t5/i-MX-Processors/How-to-control-MIPI-PHY-power-supply/m-p/672725#M103638 <HTML><HEAD></HEAD><BODY><P>Hi Ko-hey</P><P></P><P>&gt;Q1. <BR />please refer to i.MX7 RM sect.5.5.10.34 PU PGC software down trigger (GPC_PU_PGC_SW_PDN_REQ)<BR />MIPI_PHY_SW_PDN_REQ - Software power down trigger for MIPI_PHY<BR /><A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.nxp.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX7DRM.pdf" rel="nofollow" target="_blank">http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf</A></P><P></P><P>&gt;Q2. <BR />unfortunately there no way to put CPU in Deep Sleep mode with keeping LP11.<BR />According to i.MX7RM Table 5-5. Low Power Mode Definition MIPI is "OFF" except in<BR />System IDLE mode. Also please check sect.4.1.1. Use case 1: Deep-Sleep Mode (DSM)<BR />AN5383 i.MX 7DS Power Consumption Measurement</P><P></P><P>"All of the modules are disabled.<BR />All analog PHYs are powered down."<BR /><A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.nxp.com%2Fassets%2Fdocuments%2Fdata%2Fen%2Fapplication-notes%2FAN5383.pdf" rel="nofollow" target="_blank">http://cache.nxp.com/assets/documents/data/en/application-notes/AN5383.pdf</A></P><P></P><P>&gt;Q3. <BR />there is no way to maintain D-PHY LP11 with VDDA_MIPI dropped, as in LP11 state<BR />D-PHY LP transmitter should mainatin output high level (typ.1.2V).</P><P></P><P>Best regards<BR />igor<BR />-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Sun, 04 Jun 2017 23:37:16 GMT https://community.nxp.com/t5/i-MX-Processors/How-to-control-MIPI-PHY-power-supply/m-p/672725#M103638 igorpadykov 2017-06-04T23:37:16Z