<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic iMX6DL - Invert LDB clock polarity in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-Invert-LDB-clock-polarity/m-p/672036#M103551</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I'm using iMX6DL with Android 5.1.1, Linux kernel 3.14.52. I use LVDS output for display signals. These signals are converted to RGB by an external IC because I use RGB display (only LVDS signals are available from iMX6 hardware).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm looking to invert clock polarity of the RGB display. So I tried to invert LVDS clock polarity, which fail until now.&lt;BR /&gt;The display is printing the half of screen and blinking pixels. I can see if I stop/enable the good clock source. By default, PLL5 is the clock source.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ref manual Rev. 2, 04/2015.&lt;BR /&gt;- With &lt;EM&gt;regaccess&lt;/EM&gt;, I tried to change some registers, including IPU_DI0_GENERAL, bit 17, di0_polarity_disp_clk =&amp;gt; do nothing.&lt;BR /&gt;- p810, IPU1_DI0_CLK_ROOT source could be PLLs, ipp_di0_clk, ldb_di0_ipu =&amp;gt; when I switch to ldb_di0_ipu (register CHSCCDR:ipu1_di0_clk_sel), screen freezes. What is the source of ldb_di0_ipu ? Which register should I change to invert this clock source ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any advice will help.&lt;BR /&gt;Thanks, Pierre&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 01 Jun 2017 08:07:05 GMT</pubDate>
    <dc:creator>pierrelgcb</dc:creator>
    <dc:date>2017-06-01T08:07:05Z</dc:date>
    <item>
      <title>iMX6DL - Invert LDB clock polarity</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-Invert-LDB-clock-polarity/m-p/672036#M103551</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I'm using iMX6DL with Android 5.1.1, Linux kernel 3.14.52. I use LVDS output for display signals. These signals are converted to RGB by an external IC because I use RGB display (only LVDS signals are available from iMX6 hardware).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm looking to invert clock polarity of the RGB display. So I tried to invert LVDS clock polarity, which fail until now.&lt;BR /&gt;The display is printing the half of screen and blinking pixels. I can see if I stop/enable the good clock source. By default, PLL5 is the clock source.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ref manual Rev. 2, 04/2015.&lt;BR /&gt;- With &lt;EM&gt;regaccess&lt;/EM&gt;, I tried to change some registers, including IPU_DI0_GENERAL, bit 17, di0_polarity_disp_clk =&amp;gt; do nothing.&lt;BR /&gt;- p810, IPU1_DI0_CLK_ROOT source could be PLLs, ipp_di0_clk, ldb_di0_ipu =&amp;gt; when I switch to ldb_di0_ipu (register CHSCCDR:ipu1_di0_clk_sel), screen freezes. What is the source of ldb_di0_ipu ? Which register should I change to invert this clock source ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any advice will help.&lt;BR /&gt;Thanks, Pierre&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 01 Jun 2017 08:07:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-Invert-LDB-clock-polarity/m-p/672036#M103551</guid>
      <dc:creator>pierrelgcb</dc:creator>
      <dc:date>2017-06-01T08:07:05Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6DL - Invert LDB clock polarity</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-Invert-LDB-clock-polarity/m-p/672037#M103552</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Pierre&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ldb block produces waveforms like on p.16 hannstar lcd datasheet&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://boundarydevices.com/wp-content/uploads/2014/12/HSD070PWW1-B01.pdf" title="http://boundarydevices.com/wp-content/uploads/2014/12/HSD070PWW1-B01.pdf"&gt;http://boundarydevices.com/wp-content/uploads/2014/12/HSD070PWW1-B01.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;sect.6.3 Bit Mapping &amp;amp; Interface Definition and clock polarity can not be changed,&lt;/P&gt;&lt;P&gt;regardless of ipu register settings. Seems one can try to interchange LVDS0_CLK_N and P&lt;/P&gt;&lt;P&gt;of external IC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 01 Jun 2017 09:25:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6DL-Invert-LDB-clock-polarity/m-p/672037#M103552</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-06-01T09:25:46Z</dc:date>
    </item>
  </channel>
</rss>

