<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: SPI FLASH BOOT in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671751#M103481</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi James.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Currently I am having similar problem.&lt;/P&gt;&lt;P&gt;Could you tell me what happened after that?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Best regard,&lt;/SPAN&gt;&lt;BR style="color: #51626f; background-color: #ffffff;" /&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Tasuku.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 12 Oct 2017 10:19:11 GMT</pubDate>
    <dc:creator>tasukuwatanabe</dc:creator>
    <dc:date>2017-10-12T10:19:11Z</dc:date>
    <item>
      <title>SPI FLASH BOOT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671747#M103477</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;&amp;nbsp; I test the spi flash on ecspi1 in u-boot. i works with code below:&lt;/P&gt;&lt;P&gt;iomux_v3_cfg_t const ecspi1_pads[] = {&lt;BR /&gt; MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),&lt;BR /&gt; MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),&lt;BR /&gt; MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),&lt;BR /&gt; //MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(SPI_PAD_CTRL),&lt;BR /&gt; MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;it means SS2 is used as gpio but not as ss2.&lt;/P&gt;&lt;P&gt;if i use&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(SPI_PAD_CTRL),&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;sf probe always get manfuacture id as 0x00&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Flashs require the &lt;SPAN&gt;ECSPI1_SS2 stays always 0 during the access period, the below if from the datasheet of m25p32:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;"&lt;/SPAN&gt;&lt;SPAN&gt;The READ IDENTIFICATION command is terminated by driving S# HIGH at any time&lt;BR /&gt;during data output. When S# is driven HIGH, the device is put in the STANDBY POWER&lt;BR /&gt;mode and waits to be selected so that it can receive, decode, and execute commands."&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But&amp;nbsp;when i use code&amp;nbsp;MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(SPI_PAD_CTRL),&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt; &lt;SPAN&gt;ECSPI1_SS2 goes low 8 clocks to drive command and goes high about serveral clocks and goes low again to read data back. it's not fit for the timing requirement of FLASH.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;After boot, we can change the code for SPI Flash to read/write. Now the questiong coming:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;while boot from spi flash, the imx6qp chip should act as the default ecspi controller, it means it can not fetch right code to memory from spi flash. how can it boot from spi flash? &amp;nbsp;is there some special configuration on the ecspi port while booting?&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;thanks.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 03:31:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671747#M103477</guid>
      <dc:creator>jameshe1</dc:creator>
      <dc:date>2017-06-02T03:31:09Z</dc:date>
    </item>
    <item>
      <title>Re: SPI FLASH BOOT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671748#M103478</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi James&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for ss2 usage without toggling it is necessary to configure ECSPIx_CONREG[BURST_LENGTH]&lt;/P&gt;&lt;P&gt;parameter according to spi-nor requirements. Usage gpio is more convenient as it does not require&lt;/P&gt;&lt;P&gt;this tweakung. One can look at spi nor uboot driver in uboot/drivers/mtd/spi folder and add&lt;/P&gt;&lt;P&gt;configuration in setup_spi() in uboot/board/freescale/mx6sabresd/mx6sabresd.c&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 05:38:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671748#M103478</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-06-02T05:38:42Z</dc:date>
    </item>
    <item>
      <title>Re: SPI FLASH BOOT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671749#M103479</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello igor,&lt;/P&gt;&lt;P&gt;&amp;nbsp; yes, it works well in uboot, but while booting from spi flash, nothing (all&amp;nbsp;codes are located in spi flash) can be done before the cpu fetch the codes correctly from the spi flash. at this time, all registers of cpu are not configurated. is it(ecspi1_ss2) &amp;nbsp;work well also?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 07:05:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671749#M103479</guid>
      <dc:creator>jameshe1</dc:creator>
      <dc:date>2017-06-02T07:05:48Z</dc:date>
    </item>
    <item>
      <title>Re: SPI FLASH BOOT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671750#M103480</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello James&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please configure ECSPIx_CONREG[BURST_LENGTH]&lt;/P&gt;&lt;P&gt;parameter according to spi-nor datasheet.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jun 2017 10:01:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671750#M103480</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-06-02T10:01:08Z</dc:date>
    </item>
    <item>
      <title>Re: SPI FLASH BOOT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671751#M103481</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi James.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Currently I am having similar problem.&lt;/P&gt;&lt;P&gt;Could you tell me what happened after that?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Best regard,&lt;/SPAN&gt;&lt;BR style="color: #51626f; background-color: #ffffff;" /&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Tasuku.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Oct 2017 10:19:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-FLASH-BOOT/m-p/671751#M103481</guid>
      <dc:creator>tasukuwatanabe</dc:creator>
      <dc:date>2017-10-12T10:19:11Z</dc:date>
    </item>
  </channel>
</rss>

