topic Re: i.MX6q PCIe with external clock and SATA in i.MX Processors

i.MX6q PCIe with external clock and SATA

maxmar — Wed, 12 Jul 2017 14:19:12 GMT

Hi Community,

I have some problems to configure PCIe with external clock on custom board with Tq module.I used Linux 4.1.15 from rel_imx_4.1.15_1.2.0_ga with patches for i.MX6qp found in the github account Freescale/linux-fslc.

I removed from file clk-imx6q.c and pci-imz6.c the i.MX6qp check:

 if (of_property_read_u32(np, "ext_osc", &val) < 0)
 val = 0;
 /*
 * imx6qp sabresd revb board has the external osc used by pcie
 * - pll6 should be set bypass mode later in driver.
 * - lvds_clk1 should be selected as pll6 bypass src, set here.
 */
 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0
 && (val == 1))
 imx_clk_set_parent(clk[IMX6QDL_PLL6_BYPASS_SRC], clk[IMX6QDL_CLK_LVDS1_IN]);

/* Configure the PHY when 100Mhz external OSC is used as input clock */
 if (imx6_pcie->ext_osc && is_imx6qp_pcie(imx6_pcie)) {
 mdelay(4);
 pcie_phy_read(pp->dbi_base, SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO, &val);
 /* MPLL_MULTIPLIER [8:2] */

I enabled ext_osc on dts file:

    clocks {
        anaclk1 {
                compatible = "fixed-clock";
                reg = <0>;
                #clock-cells = <0>;
                clock-frequency = <100000000>;  /* 100MHz */
            };
    };
&pcie {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_pcie>;
     reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
     status = "okay";
     clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
                <&clks IMX6QDL_CLK_LVDS1_IN>,
               <&clks IMX6QDL_CLK_PCIE_REF_125M>,
               <&clks IMX6QDL_PLL6_BYPASS>,
           <&clks IMX6QDL_PLL6_BYPASS_SRC>;
     clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext", "pcie_ext_src";
     ext_osc = <1>;
};
&clks {
        assigned-clocks = <&clks IMX6QDL_PLL6_BYPASS_SRC>,
                                <&clks IMX6QDL_PLL6_BYPASS>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS1_IN>,
                                 <&clks IMX6QDL_PLL6_BYPASS_SRC>;
        assigned-clock-rates = <100000000>, <100000000>;
};

This code works correctly also for imx6q in the same way as the code present in the post IMX6 PCI with external cloks, and the pcie with external clock works correctly.

With ext_osc and PLL6 bypass I just have a problem with SATA:

[ 1.428128] ahci-imx 2200000.sata: fsl,transmit-level-mV not specified, using 00000024
[ 1.436109] ahci-imx 2200000.sata: fsl,transmit-boost-mdB not specified, using 00000480
[ 1.444165] ahci-imx 2200000.sata: fsl,transmit-atten-16ths not specified, using 00002000
[ 1.452395] ahci-imx 2200000.sata: fsl,receive-eq-mdB not specified, using 05000000
[ 1.464368] ahci-imx 2200000.sata: SSS flag set, parallel bus scan disabled
[ 1.471427] ahci-imx 2200000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[ 1.480273] ahci-imx 2200000.sata: flags: ncq sntf stag pm led clo only pmp pio slum part ccc apst
[ 1.497275] ata1: SATA max UDMA/133 mmio [mem 0x02200000-0x02203fff] port 0x100 irq 308
[ 1.980832] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 1.987877] ata1.00: ATA-8: KINGSTON SV100S264G, D110225a, max UDMA/100
[ 1.987887] ata1.00: 125045424 sectors, multi 16: LBA48 NCQ (depth 31/32)
[ 2.007108] ata1.00: configured for UDMA/100
[ 2.120347] ata1.00: exception Emask 0x12 SAct 0x8000000 SErr 0xa80500 action 0x6 frozen
[ 2.128502] ata1.00: irq_stat 0x08000000, interface fatal error
[ 2.134472] ata1: SError: { UnrecovData Proto 10B8B BadCRC LinkSeq }
[ 2.205282] ata1.00: failed command: READ FPDMA QUEUED
[ 2.210474] ata1.00: cmd 60/08:d8:00:00:00/00:00:00:00:00/40 tag 27 ncq 4096 in
[ 2.225812] ata1.00: status: { DRDY }
[ 2.229529] ata1: hard resetting link
[ 4.262827] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 4.269550] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x100)
[ 4.275874] ata1.00: revalidation failed (errno=-5)
[ 9.268823] ata1: hard resetting link
[ 9.740797] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 9.747304] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x100)
[ 9.753615] ata1.00: revalidation failed (errno=-5)
[ 9.758534] ata1: limiting SATA link speed to 1.5 Gbps
[ 14.746803] ata1: hard resetting link
[ 15.218797] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
[ 15.226149] ata1.00: failed to set xfermode (err_mask=0x100)
[ 15.231862] ata1.00: disabled
[ 15.234915] ata1: exception Emask 0x12 SAct 0x0 SErr 0x800500 action 0x6 frozen t4
[ 15.242525] ata1: irq_stat 0x08000000, interface fatal error
[ 15.248222] ata1: SError: { UnrecovData Proto LinkSeq }
[ 15.253498] ata1: hard resetting link
[ 17.390824] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
[ 17.397353] ata1: EH complete

Can anyone confirm that is possible to use SATA with PLL6 bypass and PCIE external clock ?

Re: i.MX6q PCIe with external clock and SATA

igorpadykov — Wed, 12 Jul 2017 23:16:42 GMT

Hi massimiliano

is it working in uboot, if works then reason may be shaping/amplitude

settings defined by GPR (IOMUXC_GPR13) and one can set the same

settings in linux.

Best regards
igor
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Re: i.MX6q PCIe with external clock and SATA

maxmar — Thu, 13 Jul 2017 09:20:50 GMT

Hi Igor,

Why you say is it working in uboot ? I tried to modify the GPR value with devregs and unplug - plug the disk but nothing has changed.

Re: i.MX6q PCIe with external clock and SATA

igorpadykov — Thu, 13 Jul 2017 10:30:41 GMT

Hi massimiliano

one can check if it works in uboot

i.MX6Q uboot boot from SATA

Best regards
igor

Re: i.MX6q PCIe with external clock and SATA

maxmar — Thu, 13 Jul 2017 11:30:00 GMT

Hi Igor,

the problem is related to pcie external clock and pll6 bypass. If I disable pcie and don't bypass pll6 the SATA works correctly, without any change to the GPR:

[ 1.428135] ahci-imx 2200000.sata: fsl,transmit-level-mV not specified, using 00000024
[ 1.436113] ahci-imx 2200000.sata: fsl,transmit-boost-mdB not specified, using 00000480
[ 1.444170] ahci-imx 2200000.sata: fsl,transmit-atten-16ths not specified, using 00002000
[ 1.452398] ahci-imx 2200000.sata: fsl,receive-eq-mdB not specified, using 05000000
[ 1.464919] ahci-imx 2200000.sata: SSS flag set, parallel bus scan disabled
[ 1.471969] ahci-imx 2200000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[ 1.480812] ahci-imx 2200000.sata: flags: ncq sntf stag pm led clo only pmp pio slum part ccc apst
[ 1.497847] ata1: SATA max UDMA/133 mmio [mem 0x02200000-0x02203fff] port 0x100 irq 308
[ 1.976793] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 1.985455] ata1.00: ATA-8: KINGSTON SV100S264G, D110225a, max UDMA/100
[ 1.985464] ata1.00: 125045424 sectors, multi 16: LBA48 NCQ (depth 31/32)
[ 2.003362] ata1.00: configured for UDMA/100
[ 94.548264] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null)

The sata stops working when enable pll6 bypass with the external clock for pcie. The patch referred In this post i.MX 6DQ Plus simultaneously use PCIe and ENET disable sata to make pcie works with external clocks and say:

In order to pass the pcie gen2 compliance tests on imx6qp

sd revb board, add one standalone imx6qp sd ldo pcie dtb

- disalbe fec/sata, because that the fec/sata can't work

when pll6 is in bypass mode.

NOTE: Bypass mode of pll6 is mandatory required when

external oscillator is used as pcie ref clk.

This is a hardware limitation ?

Re: i.MX6q PCIe with external clock and SATA

igorpadykov — Thu, 13 Jul 2017 12:19:42 GMT

Hi massimiliano

this may be due to jitter of external clock.

Best regards
igor

Re: i.MX6q PCIe with external clock and SATA

maxmar — Thu, 13 Jul 2017 13:25:41 GMT

Hi Igor,

For the external clock We used the IDT Clock Generators 9FGV0241AKILF to reduce the jitters for pass the pcie gen2 compliance tests.

Why iRichard Zhu in the patch for imx6qp sd revb board, says "disalbe fec/sata, because that the fec/sata can't work when pll6 is in bypass mode" ?

You can confirm that is possible to use pcie and sata togheter with external clock and pll6 bypass ?

I don't find a exhaustive description of the pll6 and the operation when is enabled the bypass.

Re: i.MX6q PCIe with external clock and SATA

igorpadykov — Thu, 13 Jul 2017 23:04:29 GMT

Hi massimiliano

it is software, there is no hardware limitation,

for description one can look at EB790 "Configuration of Phase Fractional Dividers".

Best regards
igor

Re: i.MX6q PCIe with external clock and SATA

maxmar — Fri, 11 Aug 2017 14:30:22 GMT

Hi Igor,

We found the solution. The problem was caused from jitter generated by spread spectrum enabled in the external clock chip.

thank you very much!