<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic iMX7D: Simulating LPDDR3 with Hyperlynx in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666449#M102554</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial,sans-serif; background-image: initial; background-origin: initial; background-position: initial;"&gt;I am doing pre-layout simulation in order to start the PCB design, but I have doubts. &lt;BR /&gt;1. I don't find the recommended trace impedance for the LPDDR3 memory in the hardware development guide. The recommended value is only for DDR3 memory, not for LPDDR3. Micron recommends 60 ohm for single ended and 120 ohm for differential pairs. Which value is the correct impedance for LPDDR3 memory? &lt;BR /&gt;2. The iMX7 IBIS model doesn't have the Diff pin section, it is a problem for the DDR simulation. Do you have a complete model? We added the diff pin section manually but I don't know if it is fine. I don't know the vdiff value. &lt;BR /&gt; &lt;BR /&gt;[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max &lt;BR /&gt;AF25 AE25 0.000V 0.000s NA NA &lt;BR /&gt;AG23 AG24 0.000V 0.000s NA NA &lt;BR /&gt;AC20 AB20 0.000V 0.000s NA NA &lt;BR /&gt;AD27 AC27 0.000V 0.000s NA NA &lt;BR /&gt;Y24 Y23 0.000V 0.000s NA NA &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial,sans-serif; background-image: initial; background-origin: initial; background-position: initial;"&gt;Thanks!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 04 Aug 2017 14:00:05 GMT</pubDate>
    <dc:creator>noeliascotti80</dc:creator>
    <dc:date>2017-08-04T14:00:05Z</dc:date>
    <item>
      <title>iMX7D: Simulating LPDDR3 with Hyperlynx</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666449#M102554</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial,sans-serif; background-image: initial; background-origin: initial; background-position: initial;"&gt;I am doing pre-layout simulation in order to start the PCB design, but I have doubts. &lt;BR /&gt;1. I don't find the recommended trace impedance for the LPDDR3 memory in the hardware development guide. The recommended value is only for DDR3 memory, not for LPDDR3. Micron recommends 60 ohm for single ended and 120 ohm for differential pairs. Which value is the correct impedance for LPDDR3 memory? &lt;BR /&gt;2. The iMX7 IBIS model doesn't have the Diff pin section, it is a problem for the DDR simulation. Do you have a complete model? We added the diff pin section manually but I don't know if it is fine. I don't know the vdiff value. &lt;BR /&gt; &lt;BR /&gt;[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max &lt;BR /&gt;AF25 AE25 0.000V 0.000s NA NA &lt;BR /&gt;AG23 AG24 0.000V 0.000s NA NA &lt;BR /&gt;AC20 AB20 0.000V 0.000s NA NA &lt;BR /&gt;AD27 AC27 0.000V 0.000s NA NA &lt;BR /&gt;Y24 Y23 0.000V 0.000s NA NA &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial,sans-serif; background-image: initial; background-origin: initial; background-position: initial;"&gt;Thanks!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 04 Aug 2017 14:00:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666449#M102554</guid>
      <dc:creator>noeliascotti80</dc:creator>
      <dc:date>2017-08-04T14:00:05Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D: Simulating LPDDR3 with Hyperlynx</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666450#M102555</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Noelia&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems this was already answered on ticket:&lt;/P&gt;&lt;P&gt;-recommended to follow memory&amp;nbsp; rules, published in the recent Hardware Guide &lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fassets%2Fdocuments%2Fdata%2Fen%2Fuser-guides%2FIMX7DSHDG.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/assets/documents/data/en/user-guides/IMX7DSHDG.pdf&lt;/A&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;- IBIS model does not support differential signals. One of possible approach is&lt;BR /&gt;to treat with differential signals using single-ended data. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 04 Aug 2017 23:18:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666450#M102555</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-08-04T23:18:00Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D: Simulating LPDDR3 with Hyperlynx</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666451#M102556</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;My case has never been answered.&lt;/P&gt;&lt;P&gt;- In the recent Hardware Guide there is no special recommendation for LPDDR3 memory. I think it is not the same routing DDR3 or LPDDR3.&lt;/P&gt;&lt;P&gt;- IBIS model does support differential signals. I don't understand why the iMX7 model does not have diff pin section. iMX6 model has diff pin section.&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Aug 2017 17:56:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666451#M102556</guid>
      <dc:creator>noeliascotti80</dc:creator>
      <dc:date>2017-08-07T17:56:56Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D: Simulating LPDDR3 with Hyperlynx</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666452#M102557</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;Please look at Table 19 (DDR trace routing guidelines) of&amp;nbsp;Hardware&lt;/P&gt;&lt;P&gt;Development Guide for i.MX7Dual and 7Solo Applications Processors,&lt;/P&gt;&lt;P&gt;Rev. 1, 07/2017.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 10 Aug 2017 05:34:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Simulating-LPDDR3-with-Hyperlynx/m-p/666452#M102557</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-08-10T05:34:06Z</dc:date>
    </item>
  </channel>
</rss>

