<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: MAX14830:Set RxFIFO trigger level in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MAX14830-Set-RxFIFO-trigger-level/m-p/666267#M102530</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; I think it would be better to work with fixed (size) block of data, say - half of FIFO &lt;BR /&gt;to avoid FIFO under / over flow. I mean for each interrupt whole block of data should &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;be read / written.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 22 Jun 2017 06:28:26 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-06-22T06:28:26Z</dc:date>
    <item>
      <title>MAX14830:Set RxFIFO trigger level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MAX14830-Set-RxFIFO-trigger-level/m-p/666266#M102529</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;I am facing the problem of the RX overrun in the max14830. I was trying to set the RxFIFO level to one value ( say 32 word), the value is set properly. Also enable the MAX310X_IRQ_RXFIFO_BIT&amp;nbsp;and MAX310X_IRQ_TXFIFO_BIT.&lt;/P&gt;&lt;P&gt;i.e in drivers/tty/serial/max310x.c&lt;/P&gt;&lt;P&gt;/* Enable RX, TX, CTS change interrupts */&amp;nbsp;&lt;BR /&gt;&amp;nbsp;val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT | MAX310X_IRQ_RXFIFO_BIT | MAX310X_IRQ_TXFIFO_BIT;&lt;BR /&gt;&amp;nbsp;max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;also added the trigger level,&lt;/P&gt;&lt;P&gt;max310x_port_write(port, MAX310X_FIFOTRIGLVL_REG,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MAX310X_FIFOTRIGLVL_RX(32) | MAX310X_FIFOTRIGLVL_TX(2));&lt;/P&gt;&lt;P&gt;Now when the rxdata reach the value , interrupt gerenated. But its only once. After that data is receieved more than the trigger level value, interrupt is not generate.&lt;/P&gt;&lt;P&gt;RXFIFO keep increasing data and once 128 word inside the FIFO, its RX overrun error occurs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This overrun issue is not come in 9600 baud rate. But higher baud rate. I have checked this on kernel 3.14 and 4.1 kernel.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Why could be the issue ? How we can handle this ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for the support !!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Surendra&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Jun 2017 12:24:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MAX14830-Set-RxFIFO-trigger-level/m-p/666266#M102529</guid>
      <dc:creator>surendradhobale</dc:creator>
      <dc:date>2017-06-21T12:24:10Z</dc:date>
    </item>
    <item>
      <title>Re: MAX14830:Set RxFIFO trigger level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MAX14830-Set-RxFIFO-trigger-level/m-p/666267#M102530</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; I think it would be better to work with fixed (size) block of data, say - half of FIFO &lt;BR /&gt;to avoid FIFO under / over flow. I mean for each interrupt whole block of data should &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;be read / written.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 22 Jun 2017 06:28:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MAX14830-Set-RxFIFO-trigger-level/m-p/666267#M102530</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-06-22T06:28:26Z</dc:date>
    </item>
  </channel>
</rss>

